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[Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VN
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F |
Date: |
Mon, 17 Jun 2019 15:34:02 +0100 |
Switch NEON_2RM_VABS_F away from using cpu_F0s.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a10fded1f39..a006ab498e7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1374,14 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
return statusptr;
}
-static inline void gen_vfp_neg(int dp)
-{
- if (dp)
- gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
- else
- gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
-}
-
#define VFP_GEN_ITOF(name) \
static inline void gen_vfp_##name(int dp, int neon) \
{ \
@@ -4189,8 +4181,7 @@ static int neon_2rm_is_float_op(int op)
* what we are asking here is "does the code for this case in
* the Neon for-each-pass loop use cpu_F0s?".
*/
- return (op == NEON_2RM_VNEG_F ||
- (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
+ return ((op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
op == NEON_2RM_VRINTM ||
(op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) ||
op >= NEON_2RM_VRECPE_F);
@@ -6761,7 +6752,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
gen_helper_vfp_abss(tmp, tmp);
break;
case NEON_2RM_VNEG_F:
- gen_vfp_neg(0);
+ gen_helper_vfp_negs(tmp, tmp);
break;
case NEON_2RM_VSWP:
tmp2 = neon_load_reg(rd, pass);
--
2.20.1
- [Qemu-devel] [PULL 02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM, (continued)
- [Qemu-devel] [PULL 02/24] hw/arm/boot: Diagnose layouts that put initrd or DTB off the end of RAM, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 06/24] target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 04/24] hw/arm/boot: Honour image size field in AArch64 Image format kernels, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 10/24] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 09/24] hw/intc/arm_gicv3: Fix decoding of ID register range, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 08/24] hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 11/24] target/arm: Move vfp_expand_imm() to translate.[ch], Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 15/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 12/24] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 13/24] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 14/24] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F,
Peter Maydell <=
- [Qemu-devel] [PULL 17/24] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 16/24] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US], Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 24/24] target/arm: Only implement doubles if the FPU supports them, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 18/24] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 21/24] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 19/24] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 20/24] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 23/24] target/arm: Fix typos in trans function prototypes, Peter Maydell, 2019/06/17
- [Qemu-devel] [PULL 22/24] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d, Peter Maydell, 2019/06/17
- Re: [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2019/06/17