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Re: [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms checkpatch er
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms checkpatch errors in translate.c |
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Date: |
Thu, 20 Jun 2019 13:11:53 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 6/20/19 11:19 AM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <address@hidden>
>
> Remove if-else-arms-related checkpatch errors.
>
> Signed-off-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/mips/translate.c | 106
> ++++++++++++++++++++++++++++++------------------
> 1 file changed, 66 insertions(+), 40 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 324b32a..3558b2e 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -2619,16 +2619,18 @@ static const char * const mxuregnames[] = {
> /* General purpose registers moves. */
> static inline void gen_load_gpr(TCGv t, int reg)
> {
> - if (reg == 0)
> + if (reg == 0) {
> tcg_gen_movi_tl(t, 0);
> - else
> + } else {
> tcg_gen_mov_tl(t, cpu_gpr[reg]);
> + }
> }
>
> static inline void gen_store_gpr(TCGv t, int reg)
> {
> - if (reg != 0)
> + if (reg != 0) {
> tcg_gen_mov_tl(cpu_gpr[reg], t);
> + }
> }
>
> /* Moves to/from shadow registers. */
> @@ -2636,9 +2638,9 @@ static inline void gen_load_srsgpr(int from, int to)
> {
> TCGv t0 = tcg_temp_new();
>
> - if (from == 0)
> + if (from == 0) {
> tcg_gen_movi_tl(t0, 0);
> - else {
> + } else {
> TCGv_i32 t2 = tcg_temp_new_i32();
> TCGv_ptr addr = tcg_temp_new_ptr();
>
> @@ -2841,10 +2843,11 @@ static void gen_store_fpr64(DisasContext *ctx,
> TCGv_i64 t, int reg)
>
> static inline int get_fp_bit(int cc)
> {
> - if (cc)
> + if (cc) {
> return 24 + cc;
> - else
> + } else {
> return 23;
> + }
> }
>
> /* Addresses computation */
> @@ -2908,14 +2911,16 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64
> arg)
>
> static inline void check_cp0_enabled(DisasContext *ctx)
> {
> - if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
> + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
> generate_exception_err(ctx, EXCP_CpU, 0);
> + }
> }
>
> static inline void check_cp1_enabled(DisasContext *ctx)
> {
> - if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
> + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
> generate_exception_err(ctx, EXCP_CpU, 1);
> + }
> }
>
> /* Verify that the processor is running with COP1X instructions enabled.
> @@ -2924,8 +2929,9 @@ static inline void check_cp1_enabled(DisasContext *ctx)
>
> static inline void check_cop1x(DisasContext *ctx)
> {
> - if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
> + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
> generate_exception_end(ctx, EXCP_RI);
> + }
> }
>
> /* Verify that the processor is running with 64-bit floating-point
> @@ -2933,8 +2939,9 @@ static inline void check_cop1x(DisasContext *ctx)
>
> static inline void check_cp1_64bitmode(DisasContext *ctx)
> {
> - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
> + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
> generate_exception_end(ctx, EXCP_RI);
> + }
> }
>
> /*
> @@ -2950,8 +2957,9 @@ static inline void check_cp1_64bitmode(DisasContext
> *ctx)
> */
> static inline void check_cp1_registers(DisasContext *ctx, int regs)
> {
> - if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
> + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
> generate_exception_end(ctx, EXCP_RI);
> + }
> }
>
> /* Verify that the processor is running with DSP instructions enabled.
> @@ -3040,8 +3048,9 @@ static inline void check_ps(DisasContext *ctx)
> instructions are not enabled. */
> static inline void check_mips_64(DisasContext *ctx)
> {
> - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
> + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
> generate_exception_end(ctx, EXCP_RI);
> + }
> }
> #endif
>
> @@ -3131,8 +3140,7 @@ static inline void
> check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
> !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
> !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
> !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
> - !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))
> - {
> + !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) {
> generate_exception_end(ctx, EXCP_RI);
> }
> }
> @@ -3882,22 +3890,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t
> opc,
> uimm = (uint16_t)imm;
> switch (opc) {
> case OPC_ANDI:
> - if (likely(rs != 0))
> + if (likely(rs != 0)) {
> tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
> - else
> + } else {
> tcg_gen_movi_tl(cpu_gpr[rt], 0);
> + }
> break;
> case OPC_ORI:
> - if (rs != 0)
> + if (rs != 0) {
> tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
> - else
> + } else {
> tcg_gen_movi_tl(cpu_gpr[rt], uimm);
> + }
> break;
> case OPC_XORI:
> - if (likely(rs != 0))
> + if (likely(rs != 0)) {
> tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
> - else
> + } else {
> tcg_gen_movi_tl(cpu_gpr[rt], uimm);
> + }
> break;
> case OPC_LUI:
> if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) {
> @@ -6060,8 +6071,9 @@ static void gen_compute_branch (DisasContext *ctx,
> uint32_t opc,
> }
>
> out:
> - if (insn_bytes == 2)
> + if (insn_bytes == 2) {
> ctx->hflags |= MIPS_HFLAG_B16;
> + }
> tcg_temp_free(t0);
> tcg_temp_free(t1);
> }
> @@ -6708,8 +6720,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> {
> const char *register_name = "invalid";
>
> - if (sel != 0)
> + if (sel != 0) {
> check_insn(ctx, ISA_MIPS32);
> + }
>
> switch (reg) {
> case CP0_REGISTER_00:
> @@ -7464,8 +7477,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> {
> const char *register_name = "invalid";
>
> - if (sel != 0)
> + if (sel != 0) {
> check_insn(ctx, ISA_MIPS32);
> + }
>
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> @@ -8210,8 +8224,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> {
> const char *register_name = "invalid";
>
> - if (sel != 0)
> + if (sel != 0) {
> check_insn(ctx, ISA_MIPS64);
> + }
>
> switch (reg) {
> case CP0_REGISTER_00:
> @@ -8920,8 +8935,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> {
> const char *register_name = "invalid";
>
> - if (sel != 0)
> + if (sel != 0) {
> check_insn(ctx, ISA_MIPS64);
> + }
>
> if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
> gen_io_start();
> @@ -10162,8 +10178,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext
> *ctx, uint32_t opc,
> break;
> case OPC_TLBWI:
> opn = "tlbwi";
> - if (!env->tlb->helper_tlbwi)
> + if (!env->tlb->helper_tlbwi) {
> goto die;
> + }
> gen_helper_tlbwi(cpu_env);
> break;
> case OPC_TLBINV:
> @@ -10186,20 +10203,23 @@ static void gen_cp0(CPUMIPSState *env, DisasContext
> *ctx, uint32_t opc,
> break;
> case OPC_TLBWR:
> opn = "tlbwr";
> - if (!env->tlb->helper_tlbwr)
> + if (!env->tlb->helper_tlbwr) {
> goto die;
> + }
> gen_helper_tlbwr(cpu_env);
> break;
> case OPC_TLBP:
> opn = "tlbp";
> - if (!env->tlb->helper_tlbp)
> + if (!env->tlb->helper_tlbp) {
> goto die;
> + }
> gen_helper_tlbp(cpu_env);
> break;
> case OPC_TLBR:
> opn = "tlbr";
> - if (!env->tlb->helper_tlbr)
> + if (!env->tlb->helper_tlbr) {
> goto die;
> + }
> gen_helper_tlbr(cpu_env);
> break;
> case OPC_ERET: /* OPC_ERETNC */
> @@ -10273,8 +10293,9 @@ static void gen_compute_branch1(DisasContext *ctx,
> uint32_t op,
> goto out;
> }
>
> - if (cc != 0)
> + if (cc != 0) {
> check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
> + }
>
> btarget = ctx->base.pc_next + 4 + offset;
>
> @@ -10728,10 +10749,11 @@ static void gen_movci(DisasContext *ctx, int rd,
> int rs, int cc, int tf)
> return;
> }
>
> - if (tf)
> + if (tf) {
> cond = TCG_COND_EQ;
> - else
> + } else {
> cond = TCG_COND_NE;
> + }
>
> l1 = gen_new_label();
> t0 = tcg_temp_new_i32();
> @@ -10753,10 +10775,11 @@ static inline void gen_movcf_s(DisasContext *ctx,
> int fs, int fd, int cc,
> TCGv_i32 t0 = tcg_temp_new_i32();
> TCGLabel *l1 = gen_new_label();
>
> - if (tf)
> + if (tf) {
> cond = TCG_COND_EQ;
> - else
> + } else {
> cond = TCG_COND_NE;
> + }
>
> tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
> tcg_gen_brcondi_i32(cond, t0, 0, l1);
> @@ -10774,10 +10797,11 @@ static inline void gen_movcf_d(DisasContext *ctx,
> int fs, int fd, int cc,
> TCGv_i64 fp0;
> TCGLabel *l1 = gen_new_label();
>
> - if (tf)
> + if (tf) {
> cond = TCG_COND_EQ;
> - else
> + } else {
> cond = TCG_COND_NE;
> + }
>
> tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
> tcg_gen_brcondi_i32(cond, t0, 0, l1);
> @@ -10797,10 +10821,11 @@ static inline void gen_movcf_ps(DisasContext *ctx,
> int fs, int fd,
> TCGLabel *l1 = gen_new_label();
> TCGLabel *l2 = gen_new_label();
>
> - if (tf)
> + if (tf) {
> cond = TCG_COND_EQ;
> - else
> + } else {
> cond = TCG_COND_NE;
> + }
>
> tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
> tcg_gen_brcondi_i32(cond, t0, 0, l1);
> @@ -12096,8 +12121,9 @@ static void gen_farith(DisasContext *ctx, enum
> fopcode op1,
> TCGLabel *l1 = gen_new_label();
> TCGv_i64 fp0;
>
> - if (ft != 0)
> + if (ft != 0) {
> tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
> + }
> fp0 = tcg_temp_new_i64();
> gen_load_fpr64(ctx, fp0, fs);
> gen_store_fpr64(ctx, fp0, fd);
>