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[Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec |
Date: |
Sun, 23 Jun 2019 19:04:35 +0200 |
From: Richard Henderson <address@hidden>
Detect during initialization if the emulated CPU supports Altivec,
and store the result in the flag have_isa_altivec. The definition
of Altivec SIMD instructions set evolved over time. Different
generations of Altivec will be distinguished by other flags in TCG,
and they are currently have_isa_2_06 and have_isa_3_00.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
tcg/ppc/tcg-target.h | 25 +++++++++++++++++++++++++
tcg/ppc/tcg-target.inc.c | 8 ++++++++
2 files changed, 33 insertions(+)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 690fa74..f6283f4 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -58,6 +58,7 @@ typedef enum {
TCG_AREG0 = TCG_REG_R27
} TCGReg;
+extern bool have_isa_altivec;
extern bool have_isa_2_06;
extern bool have_isa_3_00;
@@ -135,6 +136,30 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_mulsh_i64 1
#endif
+/*
+ * While technically Altivec could support V64, it has no 64-bit store
+ * instruction and substituting two 32-bit stores makes the generated
+ * code quite large.
+ */
+#define TCG_TARGET_HAS_v64 0
+#define TCG_TARGET_HAS_v128 have_isa_altivec
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_cmpsel_vec 0
+
void flush_icache_range(uintptr_t start, uintptr_t stop);
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 8e1bba7..26892de 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -64,6 +64,7 @@
static tcg_insn_unit *tb_ret_addr;
+bool have_isa_altivec;
bool have_isa_2_06;
bool have_isa_3_00;
@@ -2781,6 +2782,9 @@ static void tcg_target_init(TCGContext *s)
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
+ if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
+ have_isa_altivec = true;
+ }
if (hwcap & PPC_FEATURE_ARCH_2_06) {
have_isa_2_06 = true;
}
@@ -2792,6 +2796,10 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
+ if (have_isa_altivec) {
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
+ }
tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
--
2.7.4
- [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 06/16] tcg/ppc: Add support for vector maximum/minimum, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 09/16] tcg/ppc: Prepare case for vector multiply, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 07/16] tcg/ppc: Add support for vector add/subtract, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 10/16] tcg/ppc: Add empty file tcg-target.opc.h, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 05/16] tcg/ppc: Add support for load/store/logic/comparison, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 08/16] tcg/ppc: Add support for vector saturated add/subtract, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 01/16] tcg/ppc: Introduce Altivec registers, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 14/16] tcg/ppc: Update vector support to v2.06, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 11/16] tcg/ppc: Support vector shift by immediate, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 15/16] tcg/ppc: Update vector support to v2.07, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 13/16] tcg/ppc: Support vector dup2, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 12/16] tcg/ppc: Support vector multiply, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 16/16] tcg/ppc: Update vector support to v3.00, Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 04/16] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC(), Aleksandar Markovic, 2019/06/23
- [Qemu-devel] [PATCH v5 03/16] tcg/ppc: Introduce macro VX4(), Aleksandar Markovic, 2019/06/23
- Re: [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes, no-reply, 2019/06/23