Re: [Qemu-devel] [PATCH 07/10] hw/mips/gt64xxx_pci: Align the pci0-mem size

[Aleksandar Markovic]

On Jun 25, 2019 12:44 AM, "Philippe Mathieu-Daudé" <address@hidden> wrote:
>
> One byte is missing, use an aligned size.
>
>     (qemu) info mtree
>     memory-region: pci0-mem
>       0000000000000000-00000000fffffffe (prio 0, i/o): pci0-mem
>                                       ^
>
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
> ---

Reviewed-by: Aleksandar Markovic <address@hidden>

I agree with this change, but do we have similar situations in QEMU code
elsewhere?

>  hw/mips/gt64xxx_pci.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
> index 815ef0711d..2fa313f498 100644
> --- a/hw/mips/gt64xxx_pci.c
> +++ b/hw/mips/gt64xxx_pci.c
> @@ -23,6 +23,7 @@
>   */
>
>  #include "qemu/osdep.h"
> +#include "qemu/units.h"
>  #include "qemu/log.h"
>  #include "hw/hw.h"
>  #include "hw/mips/mips.h"
> @@ -1201,7 +1202,7 @@ PCIBus *gt64120_register(qemu_irq *pic)
>      dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
>      d = GT64120_PCI_HOST_BRIDGE(dev);
>      phb = PCI_HOST_BRIDGE(dev);
> -    memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem",
UINT32_MAX);
> +    memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
>      address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
>      phb->bus = pci_register_root_bus(dev, "pci",
>                                       gt64120_pci_set_irq,
gt64120_pci_map_irq,
> --
> 2.19.1
>
>