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[Qemu-devel] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succ
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds |
Date: |
Wed, 3 Jul 2019 01:40:21 -0700 |
From: Hesham Almatary <address@hidden>
The current implementation unnecessarily checks for PMP even if MMU translation
failed. This may trigger a wrong PMP access exception instead of
a page exception.
For example, the very first instruction fetched after the first satp write in
S-Mode will trigger a PMP access fault instead of an instruction fetch page
fault.
This patch prioritises MMU exceptions over PMP exceptions and only checks for
PMP if MMU translation succeeds. This patch is required for future commits
that properly report PMP exception violations if PTW succeeds.
Signed-off-by: Hesham Almatary <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0bbfb7f48b79..a45b05ef8395 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -436,6 +436,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
" prot %d\n", __func__, address, ret, pa, prot);
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+ (ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) {
ret = TRANSLATE_FAIL;
}
--
2.21.0
- [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 02/32] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 03/32] target/riscv: Fix PMP range boundary address bug, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 08/32] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 13/32] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/07/03
- [Qemu-devel] [PULL 15/32] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/07/03