Re: [PATCH v2 3/5] target/arm: Handle trapping to EL2 of AArch32 VMRS instructions

[Marc Zyngier]

On 2019-12-02 15:35, Richard Henderson wrote:
> On 12/1/19 12:20 PM, Marc Zyngier wrote:
> > HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
> > EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
> > In order to handle this, introduce a new TCG helper function that
> > checks for these control bits before executing the VMRC instruction.
> >
> > Tested with a hacked-up version of KVM/arm64 that sets the control
> > bits for 32bit guests.
> >
> > Reviewed-by: Edgar E. Iglesias <address@hidden>
> > Signed-off-by: Marc Zyngier <address@hidden>
> > ---
> >  target/arm/helper-a64.h        |  2 ++
> >  target/arm/translate-vfp.inc.c | 18 +++++++++++++++---
> >  target/arm/vfp_helper.c        | 29 +++++++++++++++++++++++++++++
> >  3 files changed, 46 insertions(+), 3 deletions(-)
>
> Reviewed-by: Richard Henderson <address@hidden>
>
> Annoying that there's a bug in the manual -- FPSID is listed as group 
> 0 in
> plenty of places, except in the pseudo-code for Accessing the FPSID
> which uses TID3.

Are you sure? I'm looking at DDI0487E_a, and the pseudo-code for
AArch32.CheckAdvSIMDOrFPRegisterTraps has this check:

<quote>
if (tid0 == '1' && reg == '0000')                           // FPSID
  || (tid3 == '1' && reg IN {'0101', '0110', '0111'}) then  // MVFRx
    if ELUsingAArch32(EL2) then
      AArch32.SystemAccessTrap(M32_Hyp, 0x8);    // 
Exception_AdvSIMDFPAccessTrap
    else
      AArch64.AArch32SystemAccessTrap(EL2, 0x8); // 
Exception_AdvSIMDFPAccessTrap
</quote>

which seems to do the right thing. Or have you spotted a discrepancy
somewhere else (which would be oh-so-surprising...)?

Thanks,

        M.
--
Jazz is not dead. It just smells funny...