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[PULL v2 1/3] target/mips: Fix handling of LL/SC instructions after 7dd5
From: |
Aleksandar Markovic |
Subject: |
[PULL v2 1/3] target/mips: Fix handling of LL/SC instructions after 7dd547e5ab |
Date: |
Tue, 4 Feb 2020 09:01:55 +0100 |
From: Alex Richardson <address@hidden>
After 7dd547e5ab6b31e7a0cfc182d3ad131dd55a948f the env->llval value
is loaded as an unsigned value (instead of sign-extended as before).
Therefore, the CMPXCHG in gen_st_cond() in translate.c fails if the
sign bit is set in the loaded value.
Fix this by sign-extending the llval value for the 32-bit case.
I discovered this issue because FreeBSD MIPS64 was looping forever
in an atomic helper function when trying to start /sbin/init.
Signed-off-by: Alex Richardson <address@hidden>
Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of
MMU_MODE*_SUFFIX")
Buglink: https://bugs.launchpad.net/qemu/+bug/1861605
Cc: Aurelien Jarno <address@hidden>
Cc: Aleksandar Markovic <address@hidden>
Cc: Aleksandar Rikalo <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: James Clarke <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
---
target/mips/op_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 15d05a5..467914d 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -305,7 +305,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
}
}
-#define HELPER_LD_ATOMIC(name, insn, almask) \
+#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
{ \
if (arg & almask) { \
@@ -316,12 +316,12 @@ target_ulong helper_##name(CPUMIPSState *env,
target_ulong arg, int mem_idx) \
} \
env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
env->lladdr = arg; \
- env->llval = cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
+ env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
return env->llval; \
}
-HELPER_LD_ATOMIC(ll, ldl, 0x3)
+HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))
#ifdef TARGET_MIPS64
-HELPER_LD_ATOMIC(lld, ldq, 0x7)
+HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
#endif
#undef HELPER_LD_ATOMIC
#endif
--
2.7.4
- [PULL v2 0/3] MIPS queue for February 4th, 2020, Aleksandar Markovic, 2020/02/04
- [PULL v2 1/3] target/mips: Fix handling of LL/SC instructions after 7dd547e5ab,
Aleksandar Markovic <=
- [PULL v2 2/3] target/mips: Separate CP0-related helpers into their own file, Aleksandar Markovic, 2020/02/04
- [PULL v2 3/3] target/mips: Separate FPU-related helpers into their own file, Aleksandar Markovic, 2020/02/04
- Re: [PULL v2 0/3] MIPS queue for February 4th, 2020, no-reply, 2020/02/04
- Re: [PULL v2 0/3] MIPS queue for February 4th, 2020, Peter Maydell, 2020/02/04