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[PATCH v7 08/41] target/arm: Simplify tlb_force_broadcast alternatives
From: |
Richard Henderson |
Subject: |
[PATCH v7 08/41] target/arm: Simplify tlb_force_broadcast alternatives |
Date: |
Thu, 6 Feb 2020 10:54:15 +0000 |
Rather than call to a separate function and re-compute any
parameters for the flush, simply use the correct flush
function directly.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 52 +++++++++++++++++++++------------------------
1 file changed, 24 insertions(+), 28 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 49da685b29..bf69935550 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -614,56 +614,54 @@ static void tlbiall_write(CPUARMState *env, const
ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate all (TLBIALL) */
- ARMCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
if (tlb_force_broadcast(env)) {
- tlbiall_is_write(env, NULL, value);
- return;
+ tlb_flush_all_cpus_synced(cs);
+ } else {
+ tlb_flush(cs);
}
-
- tlb_flush(CPU(cpu));
}
static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
- ARMCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
+ value &= TARGET_PAGE_MASK;
if (tlb_force_broadcast(env)) {
- tlbimva_is_write(env, NULL, value);
- return;
+ tlb_flush_page_all_cpus_synced(cs, value);
+ } else {
+ tlb_flush_page(cs, value);
}
-
- tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate by ASID (TLBIASID) */
- ARMCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
if (tlb_force_broadcast(env)) {
- tlbiasid_is_write(env, NULL, value);
- return;
+ tlb_flush_all_cpus_synced(cs);
+ } else {
+ tlb_flush(cs);
}
-
- tlb_flush(CPU(cpu));
}
static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
- ARMCPU *cpu = env_archcpu(env);
+ CPUState *cs = env_cpu(env);
+ value &= TARGET_PAGE_MASK;
if (tlb_force_broadcast(env)) {
- tlbimvaa_is_write(env, NULL, value);
- return;
+ tlb_flush_page_all_cpus_synced(cs, value);
+ } else {
+ tlb_flush_page(cs, value);
}
-
- tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
}
static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3965,11 +3963,10 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env,
const ARMCPRegInfo *ri,
int mask = vae1_tlbmask(env);
if (tlb_force_broadcast(env)) {
- tlbi_aa64_vmalle1is_write(env, NULL, value);
- return;
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
+ } else {
+ tlb_flush_by_mmuidx(cs, mask);
}
-
- tlb_flush_by_mmuidx(cs, mask);
}
static int alle1_tlbmask(CPUARMState *env)
@@ -4091,11 +4088,10 @@ static void tlbi_aa64_vae1_write(CPUARMState *env,
const ARMCPRegInfo *ri,
uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (tlb_force_broadcast(env)) {
- tlbi_aa64_vae1is_write(env, NULL, value);
- return;
+ tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
+ } else {
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
-
- tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
- [PATCH v7 00/41] target/arm: Implement ARMv8.1-VHE, Richard Henderson, 2020/02/06
- [PATCH v7 01/41] target/arm: Define isar_feature_aa64_vh, Richard Henderson, 2020/02/06
- [PATCH v7 02/41] target/arm: Enable HCR_E2H for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 03/41] target/arm: Add CONTEXTIDR_EL2, Richard Henderson, 2020/02/06
- [PATCH v7 04/41] target/arm: Add TTBR1_EL2, Richard Henderson, 2020/02/06
- [PATCH v7 06/41] target/arm: Split out vae1_tlbmask, Richard Henderson, 2020/02/06
- [PATCH v7 05/41] target/arm: Update CNTVCT_EL0 for VHE, Richard Henderson, 2020/02/06
- [PATCH v7 08/41] target/arm: Simplify tlb_force_broadcast alternatives,
Richard Henderson <=
- [PATCH v7 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*, Richard Henderson, 2020/02/06
- [PATCH v7 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2020/02/06
- [PATCH v7 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2020/02/06
- [PATCH v7 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2020/02/06
- [PATCH v7 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2020/02/06
- [PATCH v7 07/41] target/arm: Split out alle1_tlbmask, Richard Henderson, 2020/02/06
- [PATCH v7 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01], Richard Henderson, 2020/02/06
- [PATCH v7 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2020/02/06
- [PATCH v7 15/41] target/arm: Recover 4 bits from TBFLAGs, Richard Henderson, 2020/02/06
- [PATCH v7 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2020/02/06