[PATCH v4 13/16] target/i386: Add EPYC model specific handlers

[Babu Moger]

Add the new EPYC model specific handlers to fix the apicid decoding.

The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
This works fine for most standard AMD and other vendors' configurations,
but this decoding sequence does not follow that of AMD's APIC ID enumeration
strictly. In some cases this can cause CPU topology inconsistency.

When booting a guest VM, the kernel tries to validate the topology, and finds
it inconsistent with the enumeration of EPYC cpu models. The more details are
in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.

To fix the problem we need to build the topology as per the Processor
Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors.
It is available at https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip

Here is the text from the PPR.
Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], the
number of least significant bits in the Initial APIC ID that indicate core ID
within a processor, in constructing per-core CPUID masks.
Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
(MNC) that the processor could theoretically support, not the actual number of
cores that are actually implemented or enabled on the processor, as indicated
by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}

Signed-off-by: Babu Moger <address@hidden>
---
 target/i386/cpu.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 389b68d765..082865d72b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3835,6 +3835,10 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .xlevel = 0x8000001E,
         .model_id = "AMD EPYC Processor",
         .cache_info = &epyc_cache_info,
+        .apicid_from_cpu_idx = x86_apicid_from_cpu_idx_epyc,
+        .topo_ids_from_apicid = x86_topo_ids_from_apicid_epyc,
+        .apicid_from_topo_ids = x86_apicid_from_topo_ids_epyc,
+        .apicid_pkg_offset = apicid_pkg_offset_epyc,
         .versions = (X86CPUVersionDefinition[]) {
             { .version = 1 },
             {