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[Bug 1863247] Re: AArch64 EXT instruction for V register does not clear
From: |
Richard Henderson |
Subject: |
[Bug 1863247] Re: AArch64 EXT instruction for V register does not clear MSB side bits |
Date: |
Fri, 14 Feb 2020 17:51:15 -0000 |
Yep.
** Changed in: qemu
Status: New => In Progress
** Changed in: qemu
Assignee: (unassigned) => Richard Henderson (rth)
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https://bugs.launchpad.net/bugs/1863247
Title:
AArch64 EXT instruction for V register does not clear MSB side bits
Status in QEMU:
In Progress
Bug description:
On AArch64 CPU with SVE register, there seems to be a bug in the
operation when executing EXT instruction to V registers. Bits above
the 128 bits of the SVE register must be cleared to 0, but qemu-
aarch64 seems to hold the value.
Example
ext v0.16b, v1.16b v2.16b, 8
After executing above instruction, (N-1) to 128 bits of z0 register
must be 0, where N is SVE register width.
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