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[PATCH 0/4] target/arm: fix some simd writes vs sve
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From: |
Richard Henderson |
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Subject: |
[PATCH 0/4] target/arm: fix some simd writes vs sve |
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Date: |
Fri, 14 Feb 2020 11:46:39 -0800 |
The launchpad bug only mentions EXT, but I found three more
via inspection. I really should extend RISU so that we can
do AdvSIMD testing with SVE enabled...
r~
Richard Henderson (4):
target/arm: Flush high bits of sve register after AdvSIMD EXT
target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
target/arm: Flush high bits of sve register after AdvSIMD INS
target/arm/translate-a64.c | 9 +++++++++
1 file changed, 9 insertions(+)
--
2.20.1
- [PATCH 0/4] target/arm: fix some simd writes vs sve,
Richard Henderson <=
- [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT, Richard Henderson, 2020/02/14
- [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX, Richard Henderson, 2020/02/14
- [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN, Richard Henderson, 2020/02/14
- [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS, Richard Henderson, 2020/02/14
- Re: [PATCH 0/4] target/arm: fix some simd writes vs sve, Peter Maydell, 2020/02/18