Re: [PATCH 13/19] target/arm: Move VLLDM and VLSTM to vfp.decode

[Peter Maydell]

On Fri, 14 Feb 2020 at 18:16, Richard Henderson
<address@hidden> wrote:
>
> Now that we no longer have an early check for ARM_FEATURE_VFP,
> we can use the proper ISA check in trans_VLLDM_VLSTM.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/vfp.decode          |  2 ++
>  target/arm/translate-vfp.inc.c | 35 ++++++++++++++++++++++
>  target/arm/translate.c         | 53 ++++++----------------------------
>  3 files changed, 46 insertions(+), 44 deletions(-)
>
> diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
> index a67b3f29ee..592fe9e1e4 100644
> --- a/target/arm/vfp.decode
> +++ b/target/arm/vfp.decode
> @@ -242,3 +242,5 @@ VCVT_sp_int  ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 
> .... \
>               vd=%vd_sp vm=%vm_sp
>  VCVT_dp_int  ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
>               vd=%vd_sp vm=%vm_dp
> +
> +VLLDM_VLSTM  1110 1100 001 l:1 rn:4 0000 1010 0000 0000
> diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
> index f6f7601fe2..8f2b97e0e7 100644
> --- a/target/arm/translate-vfp.inc.c
> +++ b/target/arm/translate-vfp.inc.c
> @@ -2816,3 +2816,38 @@ static bool trans_VCVT_dp_int(DisasContext *s, 
> arg_VCVT_dp_int *a)
>      tcg_temp_free_ptr(fpst);
>      return true;
>  }
> +
> +/*
> + * Decode VLLDM of VLSTM are nonstandard because:

"Decode of VLLDM and VLSTM"

> + *  * if there is no FPU then these insns must NOP in
> + *    Secure state and UNDEF in Nonsecure state
> + *  * if there is an FPU then these insns do not have
> + *    the usual behaviour that disas_vfp_insn() provides of
> + *    being controlled by CPACR/NSACR enable bits or the
> + *    lazy-stacking logic.

s/disas_vfp_insn/vfp_access_check/ (we never updated this
old comment when we moved the logic as part of the decodetree
conversion).

> + */
> +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
> +{
> +    TCGv_i32 fptr;
> +
> +    if (!arm_dc_feature(s, ARM_FEATURE_M) ||
> +        !arm_dc_feature(s, ARM_FEATURE_V8)) {
> +        return false;
> +    }
> +    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
> +        /* No FPU: NOP if secure, otherwise UNDEF.  */
> +        return s->v8m_secure;
> +    }

We need to UNDEF if !v8m_secure even if there is an FPU.

> +
> +    fptr = load_reg(s, a->rn);
> +    if (a->l) {
> +        gen_helper_v7m_vlldm(cpu_env, fptr);
> +    } else {
> +        gen_helper_v7m_vlstm(cpu_env, fptr);
> +    }
> +    tcg_temp_free_i32(fptr);
> +
> +    /* End the TB, because we have updated FP control bits */
> +    s->base.is_jmp = DISAS_UPDATE;
> +    return true;
> +}

thanks
-- PMM