Re: [PATCH v2 2/3] cpu/a9mpcore: Set number of GIC priority bits to 5

[Peter Maydell]

On Fri, 21 Feb 2020 at 07:46, Sai Pavan Boddu
<address@hidden> wrote:
>
> All A9 CPUs have a GIC with 5 bits of priority.
>
> Signed-off-by: Sai Pavan Boddu <address@hidden>
> Suggested-by: Peter Maydell <address@hidden>
> ---
>  hw/cpu/a9mpcore.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
> index 1f8bc8a..b4f6a7e 100644
> --- a/hw/cpu/a9mpcore.c
> +++ b/hw/cpu/a9mpcore.c
> @@ -16,6 +16,8 @@
>  #include "hw/qdev-properties.h"
>  #include "hw/core/cpu.h"
>
> +#define A9_GIC_NUM_PRIORITY_BITS    5
> +
>  static void a9mp_priv_set_irq(void *opaque, int irq, int level)
>  {
>      A9MPPrivState *s = (A9MPPrivState *)opaque;
> @@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error 
> **errp)
>      gicdev = DEVICE(&s->gic);
>      qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
>      qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
> +    qdev_prop_set_uint32(gicdev, "num-priority-bits",
> +                         A9_GIC_NUM_PRIORITY_BITS);
>
>      /* Make the GIC's TZ support match the CPUs. We assume that
>       * either all the CPUs have TZ, or none do.

Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM