Re: [PATCH] target/arm: Implement ARMv8.3-CCIDX

[Richard Henderson]

On 2/24/20 10:26 AM, Peter Maydell wrote:
> The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers
> have a format that uses the full 64 bit width of the register, and
> adds a new CCSIDR2 register so AArch32 can get at the high 32 bits.
> 
> QEMU doesn't implement caches, so we just treat these ID registers as
> opaque values that are set to the correct constant values for each
> CPU.  The only thing we need to do is allow 64-bit values in our
> cssidr[] array and provide the CCSIDR2 accessors.
> 
> We don't set the CCIDX field in our 'max' CPU because the CCSIDR
> constant values we use are the same as the ones used by the
> Cortex-A57 and they are in the old 32-bit format. This means
> that the extra regdef added here is unused currently, but it
> means that whenever in the future we add a CPU that does need
> the new 64-bit format it will just work when we set the cssidr
> values and the ID registers for it.
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> This is to some extent just ticking off the architecture
> feature from our todo list, but it does avoid an unexpected
> surprise for whoever is the first to need to implement a
> core with ARMv8.3-CCIDX...
> 
> Based-on: address@hidden
> ("target/arm: Implement v8.3-RCPC and v8.4-RCPC")
> but only to avoid a textual conflict in cpu.h

Reviewed-by: Richard Henderson <address@hidden>


r~