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Re: [PATCH v4 1/7] target/arm: Improve masking of HCR RES0 bits
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v4 1/7] target/arm: Improve masking of HCR RES0 bits |
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Date: |
Fri, 28 Feb 2020 10:55:14 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 2/28/20 9:34 AM, Peter Maydell wrote:
> One of us is miscounting, and I don't *think* it's me...
>
> bits 63..0: ff80ff8c90000000
> bits 63..32: ff80ff8c
> bits 64..48: ff80
>
> bit 48 looks like it's 0 to me.
Oops, yes, it's me.
> You could refine the valid mask as the & of the bits which we
> do want to exist in aarch32, rather than &~ of the reserved bits:
>
> valid_mask &= TTLBIS | TOCU | TICAB | ...
>
> ?
Yes, that's a good idea.
r~
[PATCH v4 2/7] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits, Richard Henderson, 2020/02/25
[PATCH v4 3/7] target/arm: Honor the HCR_EL2.TSW bit, Richard Henderson, 2020/02/25
[PATCH v4 4/7] target/arm: Honor the HCR_EL2.TACR bit, Richard Henderson, 2020/02/25
[PATCH v4 5/7] target/arm: Honor the HCR_EL2.TPCP bit, Richard Henderson, 2020/02/25
[PATCH v4 6/7] target/arm: Honor the HCR_EL2.TPU bit, Richard Henderson, 2020/02/25