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[PATCH v3 13/21] tests/tcg/xtensa: expand madd tests
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From: |
Max Filippov |
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Subject: |
[PATCH v3 13/21] tests/tcg/xtensa: expand madd tests |
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Date: |
Wed, 8 Jul 2020 15:20:53 -0700 |
Test that madd doesn't do rounding after multiplication.
Test NaN propagation rules for FPU2000 and DFPU madd opcode.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
Changes v2->v3:
- add more infzero tests for FPU2000 and DFPU
tests/tcg/xtensa/test_fp0_arith.S | 104 ++++++++++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/tests/tcg/xtensa/test_fp0_arith.S
b/tests/tcg/xtensa/test_fp0_arith.S
index df870eb7a013..7eefc1da409d 100644
--- a/tests/tcg/xtensa/test_fp0_arith.S
+++ b/tests/tcg/xtensa/test_fp0_arith.S
@@ -146,6 +146,110 @@ test madd_s
FSR_I, FSR_I, FSR_I, FSR_I
test_end
+test madd_s_precision
+ test_op3 madd.s, f0, f1, f2, f0, 0xbf800002, 0x3f800001, 0x3f800001, \
+ 0x28800000, 0x28800000, 0x28800000, 0x28800000, \
+ FSR__, FSR__, FSR__, FSR__
+test_end
+
+#if DFPU
+test madd_s_nan_dfpu
+ /* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
+ F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
+ F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
+ FSR__, FSR__, FSR__, FSR__
+
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
+ F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
+ FSR__, FSR__, FSR__, FSR__
+
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+
+ /* inf * 0 = default NaN */
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
+ F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ /* inf * 0 + SNaN1 = QNaN1 */
+ test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ /* inf * 0 + QNaN1 = QNaN1 */
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+
+ /* madd/msub SNaN turns to QNaN and sets Invalid flag */
+ test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+test_end
+#else
+test madd_s_nan_fpu2k
+ /* FPU2000 madd/msub NaN1, NaN2, NaN3 priority: NaN2, NaN3, NaN1 */
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_1, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_1, \
+ F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_1, F32_QNAN(3), \
+ F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
+ FSR__, FSR__, FSR__, FSR__
+
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_1, \
+ F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_1, F32_QNAN(3), \
+ F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), F32_QNAN(3), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_QNAN(2), F32_QNAN(3), \
+ F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
+ FSR__, FSR__, FSR__, FSR__
+
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_QNAN(2), F32_QNAN(3), \
+ F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), F32_QNAN(2), \
+ FSR__, FSR__, FSR__, FSR__
+
+ /* inf * 0 = default NaN */
+ test_op3 madd.s, f0, f1, f2, f0, F32_1, F32_PINF, F32_0, \
+ F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
+ FSR__, FSR__, FSR__, FSR__
+ /* inf * 0 + SNaN1 = SNaN1 */
+ test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_PINF, F32_0, \
+ F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ /* inf * 0 + QNaN1 = QNaN1 */
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_PINF, F32_0, \
+ F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), F32_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+
+ /* madd/msub SNaN is preserved */
+ test_op3 madd.s, f0, f1, f2, f0, F32_SNAN(1), F32_1, F32_1, \
+ F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), F32_SNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.s, f0, f1, f2, f0, F32_QNAN(1), F32_SNAN(2), F32_1, \
+ F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), F32_SNAN(2), \
+ FSR__, FSR__, FSR__, FSR__
+test_end
+#endif
+
test msub_s
test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \
--
2.20.1
- [PATCH v3 01/21] softfloat: make NO_SIGNALING_NANS runtime property, (continued)
- [PATCH v3 01/21] softfloat: make NO_SIGNALING_NANS runtime property, Max Filippov, 2020/07/08
- [PATCH v3 02/21] softfloat: pass float_status pointer to pickNaN, Max Filippov, 2020/07/08
- [PATCH v3 03/21] softfloat: add xtensa specialization for pickNaNMulAdd, Max Filippov, 2020/07/08
- [PATCH v3 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name, Max Filippov, 2020/07/08
- [PATCH v3 05/21] target/xtensa: support copying registers up to 64 bits wide, Max Filippov, 2020/07/08
- [PATCH v3 06/21] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/08
- [PATCH v3 07/21] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/08
- [PATCH v3 08/21] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/08
- [PATCH v3 10/21] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/08
- [PATCH v3 11/21] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/08
- [PATCH v3 13/21] tests/tcg/xtensa: expand madd tests,
Max Filippov <=
- [PATCH v3 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 09/21] target/xtensa: add DFP option, registers and opcodes, Max Filippov, 2020/07/08
- [PATCH v3 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 18/21] tests/tcg/xtensa: test double precision load/store, Max Filippov, 2020/07/08
- [PATCH v3 16/21] tests/tcg/xtensa: update test_lsc for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests, Max Filippov, 2020/07/08
- [PATCH v3 15/21] tests/tcg/xtensa: update test_fp1 for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 20/21] target/xtensa: import de233_fpu core, Max Filippov, 2020/07/08
- [PATCH v3 19/21] tests/tcg/xtensa: add DFP0 arithmetic tests, Max Filippov, 2020/07/08