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[PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit
From: |
Bin Meng |
Subject: |
[PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit |
Date: |
Sat, 15 Aug 2020 00:40:46 +0800 |
From: Bin Meng <bin.meng@windriver.com>
Per the SD spec, Standard Capacity SD Memory Card (SDSC) supports
capacity up to and including 2 GiB.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/sd/sd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 51f5900..5e7fc3f 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -313,7 +313,7 @@ static void sd_ocr_powerup(void *opaque)
/* card power-up OK */
sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
- if (sd->size > 1 * GiB) {
+ if (sd->size > 2 * GiB) {
sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1);
}
}
--
2.7.4
- [PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation, (continued)
[PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit,
Bin Meng <=
[PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible, Bin Meng, 2020/08/14
[PATCH 10/18] hw/sd: Add Cadence SDHCI emulation, Bin Meng, 2020/08/14
[PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card, Bin Meng, 2020/08/14