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[RFC v4 31/70] target/riscv: rvv-1.0: iota instruction
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From: |
frank . chang |
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Subject: |
[RFC v4 31/70] target/riscv: rvv-1.0: iota instruction |
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Date: |
Mon, 17 Aug 2020 16:49:16 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0992d6ac86d..7a10fc27c5f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -596,7 +596,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111
@r2_vm
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
--
2.17.1
- Re: [RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions, (continued)
- [RFC v4 24/70] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2020/08/17
- [RFC v4 25/70] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2020/08/17
- [RFC v4 26/70] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2020/08/17
- [RFC v4 27/70] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2020/08/17
- [RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2020/08/17
- [RFC v4 29/70] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2020/08/17
- [RFC v4 30/70] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2020/08/17
- [RFC v4 31/70] target/riscv: rvv-1.0: iota instruction,
frank . chang <=
- [RFC v4 32/70] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/17
- [RFC v4 33/70] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/17
- [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/08/17
- [RFC v4 35/70] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/17
- [RFC v4 37/70] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/17