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[PULL v3 06/20] target/riscv: Clean up fmv.w.x
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From: |
Alistair Francis |
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Subject: |
[PULL v3 06/20] target/riscv: Clean up fmv.w.x |
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Date: |
Fri, 21 Aug 2020 22:40:47 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Use tcg_gen_extu_tl_i64 to avoid the ifdef.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index 832f01db6f..138e317723 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -406,11 +406,7 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a)
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
-#if defined(TARGET_RISCV64)
- tcg_gen_mov_i64(cpu_fpr[a->rd], t0);
-#else
- tcg_gen_extu_i32_i64(cpu_fpr[a->rd], t0);
-#endif
+ tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
mark_fs_dirty(ctx);
--
2.28.0
- [PULL v3 00/20] riscv-to-apply queue, Alistair Francis, 2020/08/22
- [PULL v3 05/20] target/riscv: Check nanboxed inputs in trans_rvf.inc.c, Alistair Francis, 2020/08/22
- [PULL v3 06/20] target/riscv: Clean up fmv.w.x,
Alistair Francis <=
- [PULL v3 07/20] target/riscv: check before allocating TCG temps, Alistair Francis, 2020/08/22
- [PULL v3 01/20] target/riscv: Generate nanboxed results from fp helpers, Alistair Francis, 2020/08/22
- [PULL v3 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, Alistair Francis, 2020/08/22
- [PULL v3 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/22
- [PULL v3 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c, Alistair Francis, 2020/08/22
- [PULL v3 10/20] configure: Create symbolic links for pc-bios/*.elf files, Alistair Francis, 2020/08/22
- [PULL v3 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64, Alistair Francis, 2020/08/22
- [PULL v3 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/22
- [PULL v3 11/20] roms/opensbi: Upgrade from v0.7 to v0.8, Alistair Francis, 2020/08/22
- [PULL v3 04/20] target/riscv: Check nanboxed inputs to fp helpers, Alistair Francis, 2020/08/22