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[PULL v3 16/20] target/riscv: Fix the translation of physical address
From: |
Alistair Francis |
Subject: |
[PULL v3 16/20] target/riscv: Fix the translation of physical address |
Date: |
Fri, 21 Aug 2020 22:40:57 -0700 |
From: Zong Li <zong.li@sifive.com>
The real physical address should add the 12 bits page offset. It also
causes the PMP wrong checking due to the minimum granularity of PMP is
4 byte, but we always get the physical address which is 4KB alignment,
that means, we always use the start address of the page to check PMP for
all addresses which in the same page.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<370a983d0f9e8a9a927b9bb8af5e7bc84b1bf9b1.1595924470.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..2f337e418c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -543,7 +543,8 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
target_ulong vpn = addr >> PGSHIFT;
- *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT;
+ *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
+ (addr & ~TARGET_PAGE_MASK);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
@@ -630,7 +631,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
}
}
- return phys_addr;
+ return phys_addr & TARGET_PAGE_MASK;
}
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
--
2.28.0
- [PULL v3 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, (continued)
- [PULL v3 02/20] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s, Alistair Francis, 2020/08/22
- [PULL v3 08/20] hw/riscv: sifive_u: Add a dummy L2 cache controller device, Alistair Francis, 2020/08/22
- [PULL v3 03/20] target/riscv: Generate nanboxed results from trans_rvf.inc.c, Alistair Francis, 2020/08/22
- [PULL v3 10/20] configure: Create symbolic links for pc-bios/*.elf files, Alistair Francis, 2020/08/22
- [PULL v3 09/20] riscv: Fix bug in setting pmpcfg CSR for RISCV64, Alistair Francis, 2020/08/22
- [PULL v3 12/20] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware, Alistair Francis, 2020/08/22
- [PULL v3 11/20] roms/opensbi: Upgrade from v0.7 to v0.8, Alistair Francis, 2020/08/22
- [PULL v3 04/20] target/riscv: Check nanboxed inputs to fp helpers, Alistair Francis, 2020/08/22
- [PULL v3 15/20] gitlab-ci/opensbi: Update GitLab CI to build generic platform, Alistair Francis, 2020/08/22
- [PULL v3 13/20] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u, Alistair Francis, 2020/08/22
- [PULL v3 16/20] target/riscv: Fix the translation of physical address,
Alistair Francis <=
- [PULL v3 17/20] target/riscv: Change the TLB page size depends on PMP entries., Alistair Francis, 2020/08/22
- [PULL v3 14/20] hw/riscv: spike: Change the default bios to use generic platform image, Alistair Francis, 2020/08/22
- [PULL v3 18/20] hw/intc: ibex_plic: Update the pending irqs, Alistair Francis, 2020/08/22
- [PULL v3 19/20] hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines, Alistair Francis, 2020/08/22
- [PULL v3 20/20] hw/intc: ibex_plic: Honour source priorities, Alistair Francis, 2020/08/22
- Re: [PULL v3 00/20] riscv-to-apply queue, Peter Maydell, 2020/08/23