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[PULL 30/35] target/arm: Split out gen_gvec_ool_zz
From: |
Peter Maydell |
Subject: |
[PULL 30/35] target/arm: Split out gen_gvec_ool_zz |
Date: |
Fri, 28 Aug 2020 10:24:08 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 0d5bcf6c1ed..15ad6c7d323 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -142,6 +142,16 @@ static int pred_gvec_reg_size(DisasContext *s)
return size_for_gvec(pred_full_reg_size(s));
}
+/* Invoke an out-of-line helper on 2 Zregs. */
+static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
+ int rd, int rn, int data)
+{
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vsz, vsz, data, fn);
+}
+
/* Invoke an out-of-line helper on 3 Zregs. */
static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
int rd, int rn, int rm, int data)
@@ -995,10 +1005,7 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
return false;
}
if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
- vec_full_reg_offset(s, a->rn),
- vsz, vsz, 0, fns[a->esz]);
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
}
return true;
}
@@ -2050,10 +2057,7 @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
};
if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
- vec_full_reg_offset(s, a->rn),
- vsz, vsz, 0, fns[a->esz]);
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
}
return true;
}
--
2.20.1
- [PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, (continued)
- [PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Peter Maydell, 2020/08/28
- [PULL 22/35] target/arm: Rearrange {sve,fp}_check_access assert, Peter Maydell, 2020/08/28
- [PULL 20/35] target/arm: Split out gen_gvec_fn_zz, Peter Maydell, 2020/08/28
- [PULL 23/35] target/arm: Merge do_vector2_p into do_mov_p, Peter Maydell, 2020/08/28
- [PULL 24/35] target/arm: Clean up 4-operand predicate expansion, Peter Maydell, 2020/08/28
- [PULL 26/35] target/arm: Split out gen_gvec_ool_zzzp, Peter Maydell, 2020/08/28
- [PULL 25/35] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Peter Maydell, 2020/08/28
- [PULL 28/35] target/arm: Split out gen_gvec_ool_zzp, Peter Maydell, 2020/08/28
- [PULL 27/35] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Peter Maydell, 2020/08/28
- [PULL 29/35] target/arm: Split out gen_gvec_ool_zzz, Peter Maydell, 2020/08/28
- [PULL 30/35] target/arm: Split out gen_gvec_ool_zz,
Peter Maydell <=
- [PULL 32/35] target/arm: Generalize inl_qrdmlah_* helper functions, Peter Maydell, 2020/08/28
- [PULL 31/35] target/arm: Tidy SVE tszimm shift formats, Peter Maydell, 2020/08/28
- [PULL 33/35] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd, Peter Maydell, 2020/08/28
- [PULL 34/35] target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd, Peter Maydell, 2020/08/28
- [PULL 35/35] target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd, Peter Maydell, 2020/08/28
- Re: [PULL 00/35] target-arm queue, Peter Maydell, 2020/08/28