[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [RFC 08/15] target/riscv: rvb: single-bit instructions
From: |
Richard Henderson |
Subject: |
Re: [RFC 08/15] target/riscv: rvb: single-bit instructions |
Date: |
Thu, 19 Nov 2020 13:04:17 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 11/19/20 12:35 PM, Richard Henderson wrote:
> On 11/18/20 12:29 AM, frank.chang@sifive.com wrote:
>> +static bool trans_sbset(DisasContext *ctx, arg_sbset *a)
>> +{
>> + REQUIRE_EXT(ctx, RVB);
>> + return gen_arith(ctx, a, &gen_sbset);
>> +}
>> +
>> +static bool trans_sbseti(DisasContext *ctx, arg_sbseti *a)
>> +{
>> + REQUIRE_EXT(ctx, RVB);
>> + return gen_arith_shamt_tl(ctx, a, &gen_sbset);
>> +}
>> +
>> +static bool trans_sbclr(DisasContext *ctx, arg_sbclr *a)
>> +{
>> + REQUIRE_EXT(ctx, RVB);
>> + return gen_arith(ctx, a, &gen_sbclr);
>> +}
>
> Coming back to my re-use of code thing, these should use gen_shift. That
> handles the truncate of source2 to the shift amount.
>
>> +static bool trans_sbclri(DisasContext *ctx, arg_sbclri *a)
>> +{
>> + REQUIRE_EXT(ctx, RVB);
>> + return gen_arith_shamt_tl(ctx, a, &gen_sbclr);
>> +}
>> +
>> +static bool trans_sbinv(DisasContext *ctx, arg_sbinv *a)
>> +{
>> + REQUIRE_EXT(ctx, RVB);
>> + return gen_arith(ctx, a, &gen_sbinv);
>> +}
>> +
>> +static bool trans_sbinvi(DisasContext *ctx, arg_sbinvi *a)
>> +{
>> + REQUIRE_EXT(ctx, RVB);
>> + return gen_arith_shamt_tl(ctx, a, &gen_sbinv);
>> +}
>
> I think there ought to be a gen_shifti for these.
Hmm. I just realized that gen_shifti would have a generator callback with a
constant argument, a-la tcg_gen_shli_tl.
I don't know if it's worth duplicating gen_sbclr et al for a constant argument.
And the sloi/sroi insns besides. Perhaps a gen_shifti_var helper instead?
Let me know what you think, but at the moment we're left with an incoherent set
of helpers that seem split along lines that are less than ideal.
r~
- Re: [RFC 04/15] target/riscv: rvb: logic-with-negate, (continued)
- [RFC 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/11/18
- [RFC 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/11/18
- [RFC 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/11/18
- [RFC 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/11/18
- [RFC 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/11/18
- [RFC 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/11/18
- [RFC 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/11/18
- [RFC 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/11/18
- [RFC 13/15] target/riscv: rvb: address calculation, frank . chang, 2020/11/18