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[PULL 07/23] target/arm: Implement Cortex-M55 model
From: |
Peter Maydell |
Subject: |
[PULL 07/23] target/arm: Implement Cortex-M55 model |
Date: |
Fri, 8 Jan 2021 15:36:05 +0000 |
Now that we have implemented all the features needed by the v8.1M
architecture, we can add the model of the Cortex-M55. This is the
configuration without MVE support; we'll add MVE later.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201210201433.26262-5-peter.maydell@linaro.org
---
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0013e25412f..98544db2df3 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -401,6 +401,46 @@ static void cortex_m33_initfn(Object *obj)
cpu->ctr = 0x8000c000;
}
+static void cortex_m55_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fd221; /* r0p1 */
+ cpu->revidr = 0;
+ cpu->pmsav7_dregion = 16;
+ cpu->sau_sregion = 8;
+ /*
+ * These are the MVFR* values for the FPU, no MVE configuration;
+ * we will update them later when we implement MVE
+ */
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x12100011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->isar.id_pfr0 = 0x20000030;
+ cpu->isar.id_pfr1 = 0x00000230;
+ cpu->isar.id_dfr0 = 0x10200000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00111040;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000011;
+ cpu->isar.id_isar0 = 0x01103110;
+ cpu->isar.id_isar1 = 0x02212000;
+ cpu->isar.id_isar2 = 0x20232232;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+ cpu->clidr = 0x00000000; /* caches not implemented */
+ cpu->ctr = 0x8303c003;
+}
+
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
@@ -655,6 +695,8 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
+ .class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
{ .name = "ti925t", .initfn = ti925t_initfn },
--
2.20.1
- [PULL 00/23] target-arm queue, Peter Maydell, 2021/01/08
- [PULL 01/23] intc/arm_gic: Fix gic_irq_signaling_enabled() for vCPUs, Peter Maydell, 2021/01/08
- [PULL 02/23] hw/arm/virt: Remove virt machine state 'smp_cpus', Peter Maydell, 2021/01/08
- [PULL 03/23] target/arm: Fix MTE0_ACTIVE, Peter Maydell, 2021/01/08
- [PULL 04/23] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN, Peter Maydell, 2021/01/08
- [PULL 05/23] target/arm: Correct store of FPSCR value via FPCXT_S, Peter Maydell, 2021/01/08
- [PULL 06/23] target/arm: Implement FPCXT_NS fp system register, Peter Maydell, 2021/01/08
- [PULL 07/23] target/arm: Implement Cortex-M55 model,
Peter Maydell <=
- [PULL 08/23] hw/arm/highbank: Drop dead KVM support code, Peter Maydell, 2021/01/08
- [PULL 10/23] scripts/coccinelle: New script to remove unnecessary timer_del() calls, Peter Maydell, 2021/01/08
- [PULL 09/23] util/qemu-timer: Make timer_free() imply timer_del(), Peter Maydell, 2021/01/08
- [PULL 12/23] target/arm: Remove timer_del()/timer_deinit() before timer_free(), Peter Maydell, 2021/01/08
- [PULL 11/23] Remove superfluous timer_del() calls, Peter Maydell, 2021/01/08
- [PULL 14/23] allwinner-a10-pit: Use ptimer_free() in the finalize function to avoid memleaks, Peter Maydell, 2021/01/08
- [PULL 16/23] exynos4210_pwm: Use ptimer_free() in the finalize function to avoid memleaks, Peter Maydell, 2021/01/08
- [PULL 13/23] digic-timer: Use ptimer_free() in the finalize function to avoid memleaks, Peter Maydell, 2021/01/08
- [PULL 17/23] mss-timer: Use ptimer_free() in the finalize function to avoid memleaks, Peter Maydell, 2021/01/08
- [PULL 19/23] exynos4210_mct: Use ptimer_free() in the finalize function to avoid memleaks, Peter Maydell, 2021/01/08