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[PATCH 0/4] target/riscv: Generate the GDB XML file for CSR registers dy
From: |
Bin Meng |
Subject: |
[PATCH 0/4] target/riscv: Generate the GDB XML file for CSR registers dynamically |
Date: |
Tue, 12 Jan 2021 12:52:00 +0800 |
From: Bin Meng <bin.meng@windriver.com>
At present QEMU RISC-V uses a hardcoded XML to report the feature
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
approach being used currently:
- The XML does not specify the "regnum" field of a CSR entry, hence
consecutive numbers are used by the remote GDB client to access
CSRs. In QEMU we have to maintain a map table to convert the GDB
number to the hardware number which is error prone.
- The XML contains some CSRs that QEMU does not implement at all,
which causes an "E14" response sent to remote GDB client.
Change to generate the CSR register list dynamically, based on the
availability presented in the CSR function table. This new approach
will reflect a correct list of CSRs that QEMU actually implements.
[1]
https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features
Bin Meng (4):
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
target/riscv: Add CSR name in the CSR function table
target/riscv: Generate the GDB XML file for CSR registers dynamically
target/riscv: Remove built-in GDB XML files for CSRs
default-configs/targets/riscv32-linux-user.mak | 2 +-
default-configs/targets/riscv32-softmmu.mak | 2 +-
default-configs/targets/riscv64-linux-user.mak | 2 +-
default-configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.h | 11 +
target/riscv/cpu.c | 12 +
target/riscv/csr.c | 342 ++++++++++++++++++-------
target/riscv/gdbstub.c | 308 ++++------------------
gdb-xml/riscv-32bit-csr.xml | 250 ------------------
gdb-xml/riscv-64bit-csr.xml | 250 ------------------
10 files changed, 320 insertions(+), 861 deletions(-)
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
--
2.7.4
- [PATCH 0/4] target/riscv: Generate the GDB XML file for CSR registers dynamically,
Bin Meng <=