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[PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructio
From: |
frank . chang |
Subject: |
[PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructions |
Date: |
Tue, 12 Jan 2021 17:39:22 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c | 4 ----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 523c6cf7f6d..8386f4f2aa8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2881,7 +2881,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 93ed6f54e99..a2ef6b708c8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4440,7 +4440,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4450,9 +4449,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
#define DO_NAND(N, M) (!(N & M))
--
2.17.1
- [PATCH v6 38/72] target/riscv: rvv-1.0: whole register move instructions, (continued)
- [PATCH v6 38/72] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/01/12
- [PATCH v6 39/72] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/01/12
- [PATCH v6 40/72] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/01/12
- [PATCH v6 41/72] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/01/12
- [PATCH v6 42/72] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/01/12
- [PATCH v6 43/72] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/01/12
- [PATCH v6 44/72] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/01/12
- [PATCH v6 45/72] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/01/12
- [PATCH v6 46/72] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/01/12
- [PATCH v6 47/72] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/01/12
- [PATCH v6 48/72] target/riscv: rvv-1.0: mask-register logical instructions,
frank . chang <=
- [PATCH v6 49/72] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/01/12
- [PATCH v6 50/72] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/01/12
- [PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/01/12
- [PATCH v6 52/72] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/01/12
- [PATCH v6 53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/01/12
- [PATCH v6 54/72] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/01/12
- [PATCH v6 55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/01/12
- [PATCH v6 56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/01/12
- [PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/01/12
- [PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/01/12