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[PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h
From: |
Peter Maydell |
Subject: |
[PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h |
Date: |
Tue, 12 Jan 2021 16:57:36 +0000 |
From: Leif Lindholm <leif@nuviainc.com>
Add entries present in ARM DDI 0487F.c (August 2020).
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20210108185154.8108-6-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 9c1872f2686..d8fb8c845ca 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1902,6 +1902,9 @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
FIELD(ID_AA64ISAR1, SB, 36, 4)
FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
FIELD(ID_AA64PFR0, EL0, 0, 4)
FIELD(ID_AA64PFR0, EL1, 4, 4)
@@ -1912,11 +1915,18 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
FIELD(ID_AA64PFR0, GIC, 24, 4)
FIELD(ID_AA64PFR0, RAS, 28, 4)
FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
+FIELD(ID_AA64PFR0, AMU, 44, 4)
+FIELD(ID_AA64PFR0, DIT, 48, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
FIELD(ID_AA64PFR1, BT, 0, 4)
FIELD(ID_AA64PFR1, SSBS, 4, 4)
FIELD(ID_AA64PFR1, MTE, 8, 4)
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
@@ -1930,6 +1940,8 @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
FIELD(ID_AA64MMFR0, EXS, 44, 4)
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
@@ -1939,6 +1951,8 @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
FIELD(ID_AA64MMFR1, PAN, 20, 4)
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
FIELD(ID_AA64MMFR2, CNP, 0, 4)
FIELD(ID_AA64MMFR2, UAO, 4, 4)
@@ -1965,6 +1979,7 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
FIELD(ID_AA64DFR0, PMSVER, 32, 4)
FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
FIELD(ID_DFR0, COPDBG, 0, 4)
FIELD(ID_DFR0, COPSDBG, 4, 4)
--
2.20.1
- [PULL 00/21] target-arm queue, Peter Maydell, 2021/01/12
- [PULL 02/21] target/arm: enable Small Translation tables in max CPU, Peter Maydell, 2021/01/12
- [PULL 01/21] target/arm: ARMv8.4-TTST extension, Peter Maydell, 2021/01/12
- [PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name, Peter Maydell, 2021/01/12
- [PULL 04/21] target/arm: make ARMCPU.clidr 64-bit, Peter Maydell, 2021/01/12
- [PULL 05/21] target/arm: make ARMCPU.ctr 64-bit, Peter Maydell, 2021/01/12
- [PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Peter Maydell, 2021/01/12
- [PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h,
Peter Maydell <=
- [PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h, Peter Maydell, 2021/01/12
- [PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build, Peter Maydell, 2021/01/12
- [PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns, Peter Maydell, 2021/01/12
- [PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value, Peter Maydell, 2021/01/12
- [PULL 11/21] docs: Build and install all the docs in a single manual, Peter Maydell, 2021/01/12
- [PULL 09/21] ui/cocoa: Update path to docs in build tree, Peter Maydell, 2021/01/12
- [PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets, Peter Maydell, 2021/01/12
- [PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock, Peter Maydell, 2021/01/12
- [PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module, Peter Maydell, 2021/01/12
- [PULL 18/21] hw/misc: Add a PWM module for NPCM7XX, Peter Maydell, 2021/01/12