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[RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CON
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value |
Date: |
Tue, 12 Jan 2021 19:35:23 +0100 |
When the block is disabled, all registers are reset with the
exception of the ECSPI_CONREG. It is initialized to zero
when the instance is created.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
chapter 21.7.3: Control Register (ECSPIx_CONREG)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/ssi/imx_spi.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index bcc535f2893..96aecc8fa28 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -232,12 +232,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
static void imx_spi_reset(DeviceState *dev)
{
IMXSPIState *s = IMX_SPI(dev);
+ unsigned i;
trace_imx_spi_reset();
- memset(s->regs, 0, sizeof(s->regs));
-
- s->regs[ECSPI_STATREG] = 0x00000003;
+ for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
+ switch (i) {
+ case ECSPI_CONREG:
+ /* CONREG is not updated on reset */
+ break;
+ case ECSPI_STATREG:
+ s->regs[i] = 0x00000003;
+ break;
+ default:
+ s->regs[i] = 0;
+ break;
+ }
+ }
imx_spi_rxfifo_reset(s);
imx_spi_txfifo_reset(s);
--
2.26.2
- [RFC PATCH v6 01/11] hw/ssi: imx_spi: Use a macro for number of chip selects supported, (continued)
- [RFC PATCH v6 05/11] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value,
Philippe Mathieu-Daudé <=
- [RFC PATCH v6 06/11] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled, Philippe Mathieu-Daudé, 2021/01/12
- [RFC PATCH v6 07/11] hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled, Philippe Mathieu-Daudé, 2021/01/12
- [RFC PATCH v6 08/11] hw/ssi: imx_spi: Disable chip selects when controller is disabled, Philippe Mathieu-Daudé, 2021/01/12
- [RFC PATCH v6 09/11] hw/ssi: imx_spi: Round up the burst length to be multiple of 8, Philippe Mathieu-Daudé, 2021/01/12
- [RFC PATCH v6 10/11] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic, Philippe Mathieu-Daudé, 2021/01/12
- [RFC PATCH v6 11/11] hw/ssi: imx_spi: Correct tx and rx fifo endianness, Philippe Mathieu-Daudé, 2021/01/12
- Re: [RFC PATCH v6 00/11] hw/ssi: imx_spi: Fix various bugs in the imx_spi model, Bin Meng, 2021/01/12