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[PULL 21/33] target/arm: enable Secure EL2 in max CPU
From: |
Peter Maydell |
Subject: |
[PULL 21/33] target/arm: enable Secure EL2 in max CPU |
Date: |
Tue, 19 Jan 2021 15:10:52 +0000 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-18-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index dbd06ccc24c..5e851028c59 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -665,6 +665,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64pfr1;
--
2.20.1
- [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2, (continued)
- [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2, Peter Maydell, 2021/01/19
- [PULL 06/33] target/arm: use arm_is_el2_enabled() where applicable, Peter Maydell, 2021/01/19
- [PULL 04/33] target/arm: remove redundant tests, Peter Maydell, 2021/01/19
- [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2, Peter Maydell, 2021/01/19
- [PULL 08/33] target/arm: factor MDCR_EL2 common handling, Peter Maydell, 2021/01/19
- [PULL 13/33] target/arm: handle VMID change in secure state, Peter Maydell, 2021/01/19
- [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table, Peter Maydell, 2021/01/19
- [PULL 15/33] target/arm: translate NS bit in page-walks, Peter Maydell, 2021/01/19
- [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers, Peter Maydell, 2021/01/19
- [PULL 17/33] target/arm: secure stage 2 translation regime, Peter Maydell, 2021/01/19
- [PULL 21/33] target/arm: enable Secure EL2 in max CPU,
Peter Maydell <=
- [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup, Peter Maydell, 2021/01/19
- [PULL 16/33] target/arm: generalize 2-stage page-walk condition, Peter Maydell, 2021/01/19
- [PULL 18/33] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, Peter Maydell, 2021/01/19
- [PULL 22/33] target/arm: refactor vae1_tlbmask(), Peter Maydell, 2021/01/19
- [PULL 24/33] target/arm: Update PFIRST, PNEXT for pred_desc, Peter Maydell, 2021/01/19
- [PULL 25/33] target/arm: Update ZIP, UZP, TRN for pred_desc, Peter Maydell, 2021/01/19
- [PULL 23/33] target/arm: Introduce PREDDESC field definitions, Peter Maydell, 2021/01/19
- [PULL 20/33] target/arm: Implement SCR_EL2.EEL2, Peter Maydell, 2021/01/19
- [PULL 19/33] target/arm: revector to run-time pick target EL, Peter Maydell, 2021/01/19
- [PULL 27/33] hw/misc/pvpanic: split-out generic and bus dependent code, Peter Maydell, 2021/01/19