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[PATCH v3 0/9] hw/riscv: sifive_u: Add missing SPI support
From: |
Bin Meng |
Subject: |
[PATCH v3 0/9] hw/riscv: sifive_u: Add missing SPI support |
Date: |
Tue, 26 Jan 2021 13:59:58 +0800 |
From: Bin Meng <bin.meng@windriver.com>
This adds the missing SPI support to the `sifive_u` machine in the QEMU
mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU `sifive_u` out of the box. This allows users to
develop and test the recommended RISC-V boot flow with a real world use
case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,
then U-Boot SPL loads the payload from SD card or SPI flash that is a
combination of OpenSBI fw_dynamic firmware and U-Boot proper.
The m25p80 model is updated to support ISSI flash series. A bunch of
ssi-sd issues are fixed, and writing to SD card in SPI mode is supported.
Note the ssi-sd changes are split out of this series in v3, so that all
patches in v3 can go via Alistair's riscv tree.
Part of the ssi-sd changes are now in qemu/master. The remaining patches
are http://patchwork.ozlabs.org/project/qemu-devel/list/?series=226136
that will go via Philippe's sd tree.
reST documentation for RISC-V is added. Currently only `sifive_u`
machine is documented, but more to come.
Changes in v3:
- Simplify flush txfifo logic
- Convert sifive_u.rst from UTF-8 to ASCII
Changes in v2:
- Mention QPI (Quad Peripheral Interface) mode is not supported
- Log guest error when trying to write reserved registers
- Log guest error when trying to access out-of-bounds registers
- log guest error when writing to reserved bits for chip select
registers and watermark registers
- Log unimplemented warning when trying to write direct-map flash
interface registers
- Add test tx fifo full logic in sifive_spi_read(), hence remove
setting the tx fifo full flag in sifive_spi_write().
- Populate register with their default value
- Correct the "connects" typo in the commit message
- Mention in the commit message that <reg> property does not populate
the second group which represents the memory mapped address of the
SPI flash
- Correct the "connects" typo in the commit message
- Correct several typos in sifive_u.rst
- Update doc to mention U-Boot v2021.01
Bin Meng (9):
hw/block: m25p80: Add ISSI SPI flash support
hw/block: m25p80: Add various ISSI flash information
hw/ssi: Add SiFive SPI controller support
hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
docs/system: Sort targets in alphabetical order
docs/system: Add RISC-V documentation
docs/system: riscv: Add documentation for sifive_u machine
docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++++++++++++++
docs/system/target-riscv.rst | 72 +++++++
docs/system/targets.rst | 20 +-
include/hw/riscv/sifive_u.h | 9 +-
include/hw/ssi/sifive_spi.h | 47 +++++
hw/block/m25p80.c | 57 +++++-
hw/riscv/sifive_u.c | 91 +++++++++
hw/ssi/sifive_spi.c | 358 +++++++++++++++++++++++++++++++++
hw/riscv/Kconfig | 3 +
hw/ssi/Kconfig | 4 +
hw/ssi/meson.build | 1 +
11 files changed, 989 insertions(+), 9 deletions(-)
create mode 100644 docs/system/riscv/sifive_u.rst
create mode 100644 docs/system/target-riscv.rst
create mode 100644 include/hw/ssi/sifive_spi.h
create mode 100644 hw/ssi/sifive_spi.c
--
2.25.1
- [PATCH v3 0/9] hw/riscv: sifive_u: Add missing SPI support,
Bin Meng <=
- [PATCH v3 1/9] hw/block: m25p80: Add ISSI SPI flash support, Bin Meng, 2021/01/26
- [PATCH v3 2/9] hw/block: m25p80: Add various ISSI flash information, Bin Meng, 2021/01/26
- [PATCH v3 3/9] hw/ssi: Add SiFive SPI controller support, Bin Meng, 2021/01/26
- [PATCH v3 4/9] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Bin Meng, 2021/01/26
- [PATCH v3 5/9] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Bin Meng, 2021/01/26
- [PATCH v3 6/9] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value, Bin Meng, 2021/01/26
- [PATCH v3 7/9] docs/system: Sort targets in alphabetical order, Bin Meng, 2021/01/26
- [PATCH v3 8/9] docs/system: Add RISC-V documentation, Bin Meng, 2021/01/26