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[PULL 02/46] target/arm: Conditionalize DBGDIDR
From: |
Peter Maydell |
Subject: |
[PULL 02/46] target/arm: Conditionalize DBGDIDR |
Date: |
Fri, 29 Jan 2021 10:59:28 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Only define the register if it exists for the cpu.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210120031656.737646-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 417777d4bed..677a4aa79e7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6567,11 +6567,21 @@ static void define_debug_regs(ARMCPU *cpu)
*/
int i;
int wrps, brps, ctx_cmps;
- ARMCPRegInfo dbgdidr = {
- .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL0_R, .accessfn = access_tda,
- .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
- };
+
+ /*
+ * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
+ * use AArch32. Given that bit 15 is RES1, if the value is 0 then
+ * the register must not exist for this cpu.
+ */
+ if (cpu->isar.dbgdidr != 0) {
+ ARMCPRegInfo dbgdidr = {
+ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
+ .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .accessfn = access_tda,
+ .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
+ };
+ define_one_arm_cp_reg(cpu, &dbgdidr);
+ }
/* Note that all these register fields hold "number of Xs minus 1". */
brps = arm_num_brps(cpu);
@@ -6580,7 +6590,6 @@ static void define_debug_regs(ARMCPU *cpu)
assert(ctx_cmps <= brps);
- define_one_arm_cp_reg(cpu, &dbgdidr);
define_arm_cp_regs(cpu, debug_cp_reginfo);
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
--
2.20.1
- [PULL 00/46] target-arm queue, Peter Maydell, 2021/01/29
- [PULL 05/46] arm-virt: refactor gpios creation, Peter Maydell, 2021/01/29
- [PULL 01/46] target/arm: Implement ID_PFR2, Peter Maydell, 2021/01/29
- [PULL 03/46] arm: rename xlnx-zcu102.canbusN properties, Peter Maydell, 2021/01/29
- [PULL 06/46] arm-virt: add secure pl061 for reset/power down, Peter Maydell, 2021/01/29
- [PULL 02/46] target/arm: Conditionalize DBGDIDR,
Peter Maydell <=
- [PULL 09/46] configure: Move preadv check to meson.build, Peter Maydell, 2021/01/29
- [PULL 11/46] osdep: build with non-working system() function, Peter Maydell, 2021/01/29
- [PULL 07/46] hw/misc: Fix arith overflow in NPCM7XX PWM module, Peter Maydell, 2021/01/29
- [PULL 08/46] target/arm: Replace magic value by MMU_DATA_LOAD definition, Peter Maydell, 2021/01/29
- [PULL 04/46] hw: gpio: implement gpio-pwr driver for qemu reset/poweroff, Peter Maydell, 2021/01/29
- [PULL 13/46] darwin: fix cross-compiling for Darwin, Peter Maydell, 2021/01/29
- [PULL 10/46] configure: cross-compiling with empty cross_prefix, Peter Maydell, 2021/01/29
- [PULL 12/46] darwin: remove redundant dependency declaration, Peter Maydell, 2021/01/29
- [PULL 14/46] configure: cross compile should use x86_64 cpu_family, Peter Maydell, 2021/01/29
- [PULL 16/46] darwin: remove 64-bit build detection on 32-bit OS, Peter Maydell, 2021/01/29