Re: [PATCH v2 17/22] target/loongarch: Add floating point load/store instruction translation

[Richard Henderson]

On 7/20/21 11:53 PM, Song Gao wrote:
> +static bool trans_fldx_d(DisasContext *ctx, arg_fldx_d *a)
> +{
> +    TCGv t0;
> +    TCGv_i64 fp0;
> +    TCGv Rj = cpu_gpr[a->rj];
> +    TCGv Rk = cpu_gpr[a->rk];
> +
> +    t0 = tcg_temp_new();
> +    fp0 = tcg_temp_new_i64();
> +
> +    if (a->rj == 0 && a->rk == 0) {
> +        /* Nop */
> +        return true;
> +    }

This is not true.  This is simply a read from address 0 + 0 = 0.
Similarly for all of the other indexed memory operations.

And again, you should be using helpers to reduce the replication here.


r~