Re: [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension

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Re: [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension

From:	Richard Henderson
Subject:	Re: [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension
Date:	Mon, 23 Aug 2021 10:17:19 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 8/23/21 9:40 AM, Philipp Tomsich wrote:

+static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
+{
+    REQUIRE_ZBC(ctx);
+
+    /* Perform a clmulr ... */
+    gen_arith(ctx, a, gen_helper_clmulr);
+
+    /* ... then shift the result 1 bit to the right. */
+    TCGv dst = tcg_temp_new();
+    gen_get_gpr(dst, a->rd);
+    tcg_gen_shri_tl(dst, dst, 1);
+    gen_set_gpr(a->rd, dst);
+    tcg_temp_free(dst);

I think it would be better to place the shift into a helper, so that you leave all of thegpr manipulation to gen_arith.


E.g.

static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
{
    gen_helper_clmulr(dst, src1, src2);
    tcg_gen_shri_tl(dst, dst, 1);
}


r~

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Re: [PATCH v3 05/15] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), (continued)
- [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Richard Henderson, 2021/08/23
- [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 06/15] target/riscv: Reassign instructions to the Zbs-extension, Richard Henderson, 2021/08/23
- [PATCH v3 10/15] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 10/15] target/riscv: Add a REQUIRE_32BIT macro, Richard Henderson, 2021/08/23
- [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 12/15] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Richard Henderson, 2021/08/23
- [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 07/15] target/riscv: Add instructions of the Zbc-extension, Richard Henderson <=
- [PATCH v3 08/15] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 08/15] target/riscv: Reassign instructions to the Zbb-extension, Richard Henderson, 2021/08/23
- [PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec, Richard Henderson, 2021/08/23
- [PATCH v3 09/15] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 09/15] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Richard Henderson, 2021/08/23
- [PATCH v3 15/15] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/08/23
- [PATCH v3 11/15] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/08/23
  - Re: [PATCH v3 11/15] target/riscv: Add rev8 instruction, removing grev/grevi, Richard Henderson, 2021/08/23
- [PATCH v3 13/15] target/riscv: Remove RVB (replaced by Zb[abcs], Philipp Tomsich, 2021/08/23

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