[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAdd
|
From: |
Philippe Mathieu-Daudé |
|
Subject: |
[PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr |
|
Date: |
Wed, 25 Aug 2021 15:01:57 +0200 |
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.
Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>
---
target/mips/cpu-defs.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index c6ab3af190e..cbc45fcb0e8 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -828,7 +828,7 @@ const mips_def_t mips_defs[] =
(0x1 << FCR0_D) | (0x1 << FCR0_S),
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
- .SEGBITS = 42,
+ .SEGBITS = 48,
.PABITS = 48,
.insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
ASE_LMMI | ASE_LEXT,
--
2.31.1
- [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions, (continued)
- [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 06/28] target/mips: Introduce generic TRANS() macro for decodetree helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 05/28] target/mips: Rename 'rtype' as 'r', Philippe Mathieu-Daudé, 2021/08/25
- [PULL 07/28] target/mips: Extract NEC Vr54xx helper definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 11/28] target/mips: Convert Vr54xx MUL* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr,
Philippe Mathieu-Daudé <=
- [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 16/28] target/mips: Remove gen_helper_0e3i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 17/28] target/mips: Remove gen_helper_1e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 21/28] target/mips: Inline gen_helper_0e0i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_err(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 23/28] target/mips: Define gen_helper() macros in translate.h, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 24/28] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers, Philippe Mathieu-Daudé, 2021/08/25