Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instruc

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Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instruc

From:	Richard Henderson
Subject:	Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions
Date:	Mon, 30 Aug 2021 19:30:20 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 8/30/21 10:16 AM, Frédéric Pétrot wrote:

+void tcg_gen_ext_i64_i128(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg)
+{
+    tcg_gen_mov_i64(lo, arg);
+    tcg_gen_sari_i64(hi, arg, 63);
+}


No, don't add this until we add TCGv_i128.
Just use sari as needed in target/riscv when dealing with TCGv_i64.


r~

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[PATCH 1/8] target/riscv: Settings for 128-bit extension support, Frédéric Pétrot, 2021/08/30
- [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Frédéric Pétrot, 2021/08/30
  - Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Philippe Mathieu-Daudé, 2021/08/30
  - Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Richard Henderson, 2021/08/30
    - Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Frédéric Pétrot, 2021/08/31
  - Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions, Richard Henderson <=
- [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Frédéric Pétrot, 2021/08/30
  - Re: [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Philippe Mathieu-Daudé, 2021/08/30
    - Re: [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Philippe Mathieu-Daudé, 2021/08/30
    - Re: [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Frédéric Pétrot, 2021/08/31
    - Re: [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Richard Henderson, 2021/08/30
  - Re: [PATCH 4/8] target/riscv: 128-bit arithmetic and logic instructions, Richard Henderson, 2021/08/30
- [PATCH 2/8] target/riscv: 128-bit registers creation and access, Frédéric Pétrot, 2021/08/30
  - Re: [PATCH 2/8] target/riscv: 128-bit registers creation and access, Philippe Mathieu-Daudé, 2021/08/30
- [PATCH 6/8] target/riscv: Support of compiler's 128-bit integer types, Frédéric Pétrot, 2021/08/30
  - Re: [PATCH 6/8] target/riscv: Support of compiler's 128-bit integer types, Richard Henderson, 2021/08/30

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