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[PATCH v2 07/20] ppc/pnv: Add POWER10 quads
From: |
Cédric Le Goater |
Subject: |
[PATCH v2 07/20] ppc/pnv: Add POWER10 quads |
Date: |
Thu, 2 Sep 2021 15:09:15 +0200 |
and use a pnv_chip_power10_quad_realize() helper to avoid code
duplication with P9. This still needs some refinements on the XSCOM
registers handling in PnvQuad.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
v2: rebased on previous changes adding 'quad-id'
include/hw/ppc/pnv.h | 3 +++
hw/ppc/pnv.c | 50 +++++++++++++++++++++++++++++++++++---------
2 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index a299fbc7f25c..13495423283a 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -128,6 +128,9 @@ struct Pnv10Chip {
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
+
+ uint32_t nr_quads;
+ PnvQuad *quads;
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a186df3fee41..5c342e313329 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1370,6 +1370,21 @@ static void pnv_chip_power9_instance_init(Object *obj)
chip->num_phbs = pcc->num_phbs;
}
+static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
+ PnvCore *pnv_core)
+{
+ char eq_name[32];
+ int core_id = CPU_CORE(pnv_core)->core_id;
+
+ snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
+ object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
+ sizeof(*eq), TYPE_PNV_QUAD,
+ &error_fatal, NULL);
+
+ object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
+ qdev_realize(DEVICE(eq), NULL, &error_fatal);
+}
+
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip9);
@@ -1379,18 +1394,9 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error
**errp)
chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
for (i = 0; i < chip9->nr_quads; i++) {
- char eq_name[32];
PnvQuad *eq = &chip9->quads[i];
- PnvCore *pnv_core = chip->cores[i * 4];
- int core_id = CPU_CORE(pnv_core)->core_id;
-
- snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
- object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
- sizeof(*eq), TYPE_PNV_QUAD,
- &error_fatal, NULL);
- object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
- qdev_realize(DEVICE(eq), NULL, &error_fatal);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
@@ -1606,6 +1612,24 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
}
+static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
+{
+ PnvChip *chip = PNV_CHIP(chip10);
+ int i;
+
+ chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
+ chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
+
+ for (i = 0; i < chip10->nr_quads; i++) {
+ PnvQuad *eq = &chip10->quads[i];
+
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
+ &eq->xscom_regs);
+ }
+}
+
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
@@ -1627,6 +1651,12 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
return;
}
+ pnv_chip_power10_quad_realize(chip10, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
/* XIVE2 interrupt controller (POWER10) */
object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
PNV10_XIVE2_IC_BASE(chip), &error_fatal);
--
2.31.1
- [PATCH v2 18/20] xive2: Add a get_config() handler for the router configuration, (continued)
- [PATCH v2 18/20] xive2: Add a get_config() handler for the router configuration, Cédric Le Goater, 2021/09/02
- [PATCH v2 20/20] pnv/xive2: Add support for 8bits thread id, Cédric Le Goater, 2021/09/02
- [PATCH v2 02/20] ppc/pnv: Add an assert when calculating the RAM distribution on chips, Cédric Le Goater, 2021/09/02
- [PATCH v2 03/20] ppc/xive2: Introduce a XIVE2 core framework, Cédric Le Goater, 2021/09/02
- [PATCH v2 04/20] ppc/xive2: Introduce a presenter matching routine, Cédric Le Goater, 2021/09/02
- [PATCH v2 01/20] docs/system: ppc: Update the URL for OpenPOWER firmware images, Cédric Le Goater, 2021/09/02
- [PATCH v2 07/20] ppc/pnv: Add POWER10 quads,
Cédric Le Goater <=
- [PATCH v2 08/20] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge, Cédric Le Goater, 2021/09/02
- [PATCH v2 09/20] ppc/pnv: Add a HOMER model to POWER10, Cédric Le Goater, 2021/09/02
- [PATCH v2 05/20] ppc/pnv: Add a XIVE2 controller to the POWER10 chip, Cédric Le Goater, 2021/09/02
- [PATCH v2 12/20] ppc/xive: Add support for PQ state bits offload, Cédric Le Goater, 2021/09/02
- [PATCH v2 14/20] ppc/pnv: Add support for PHB5 "Address-based trigger" mode, Cédric Le Goater, 2021/09/02
- [PATCH v2 06/20] ppc/pnv: Add a OCC model for POWER10, Cédric Le Goater, 2021/09/02
- [PATCH v2 16/20] ppc/pnv: add XIVE Gen2 TIMA support, Cédric Le Goater, 2021/09/02