Re: [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if s

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Re: [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if s

From:	Richard Henderson
Subject:	Re: [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits
Date:	Fri, 3 Sep 2021 20:45:01 +0200
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 9/3/21 7:00 PM, Philipp Tomsich wrote:

@@ -652,5 +652,15 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw 
*a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_ZBA(ctx);
+
+    /*
+     * The shamt field is only 6 bits for RV64 (with the 7th bit
+     * remaining reserved for RV128).  If the reserved bit is set
+     * on RV64, the encoding is illegal.
+     */
+    if (a->shamt >= TARGET_LONG_BITS) {
+        return false;
+    }
+
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);


As previously stated, drop this patch.
It is done correctly inside gen_shift_imm_fn.


r~

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[PATCH v9 00/14] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/09/03
- [PATCH v9 02/14] target/riscv: Reassign instructions to the Zba-extension, Philipp Tomsich, 2021/09/03
  - Re: [PATCH v9 02/14] target/riscv: Reassign instructions to the Zba-extension, Richard Henderson, 2021/09/03
- [PATCH v9 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Philipp Tomsich, 2021/09/03
- [PATCH v9 06/14] target/riscv: Reassign instructions to the Zbs-extension, Philipp Tomsich, 2021/09/03
- [PATCH v9 09/14] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/09/03
- [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Philipp Tomsich, 2021/09/03
  - Re: [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Richard Henderson <=
    - Re: [PATCH v9 03/14] target/riscv: slli.uw is only a valid encoding if shamt first in 64 bits, Philipp Tomsich, 2021/09/03
- [PATCH v9 08/14] target/riscv: Reassign instructions to the Zbb-extension, Philipp Tomsich, 2021/09/03
- [PATCH v9 11/14] target/riscv: Add rev8 instruction, removing grev/grevi, Philipp Tomsich, 2021/09/03
- [PATCH v9 07/14] target/riscv: Add instructions of the Zbc-extension, Philipp Tomsich, 2021/09/03
- [PATCH v9 04/14] target/riscv: Remove the W-form instructions from Zbs, Philipp Tomsich, 2021/09/03
- [PATCH v9 01/14] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/09/03
- [PATCH v9 10/14] target/riscv: Add a REQUIRE_32BIT macro, Philipp Tomsich, 2021/09/03
- [PATCH v9 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Philipp Tomsich, 2021/09/03
- [PATCH v9 13/14] target/riscv: Remove RVB (replaced by Zb[abcs], Philipp Tomsich, 2021/09/03
- [PATCH v9 14/14] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/09/03

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