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[PATCH v2 08/30] tcg/loongarch64: Implement the memory barrier op
From: |
WANG Xuerui |
Subject: |
[PATCH v2 08/30] tcg/loongarch64: Implement the memory barrier op |
Date: |
Wed, 22 Sep 2021 04:18:53 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch64/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 69e882ba5d..338b772732 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -234,3 +234,35 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
g_assert_not_reached();
}
}
+
+#include "tcg-insn-defs.c.inc"
+
+/*
+ * TCG intrinsics
+ */
+
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ /* Baseline LoongArch only has the full barrier, unfortunately. */
+ tcg_out_opc_dbar(s, 0);
+}
+
+/*
+ * Entry-points
+ */
+
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
+{
+ TCGArg a0 = args[0];
+
+ switch (opc) {
+ case INDEX_op_mb:
+ tcg_out_mb(s, a0);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
--
2.33.0
- Re: [PATCH v2 06/30] tcg/loongarch64: Define the operand constraints, (continued)
[PATCH v2 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/21
[PATCH v2 08/30] tcg/loongarch64: Implement the memory barrier op,
WANG Xuerui <=
[PATCH v2 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets, WANG Xuerui, 2021/09/21
[PATCH v2 10/30] tcg/loongarch64: Implement goto_ptr, WANG Xuerui, 2021/09/21
[PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops, WANG Xuerui, 2021/09/21
[PATCH v2 11/30] tcg/loongarch64: Implement sign-/zero-extension ops, WANG Xuerui, 2021/09/21
[PATCH v2 13/30] tcg/loongarch64: Implement deposit/extract ops, WANG Xuerui, 2021/09/21
[PATCH v2 15/30] tcg/loongarch64: Implement clz/ctz ops, WANG Xuerui, 2021/09/21