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[PATCH v6 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem
From: |
WANG Xuerui |
Subject: |
[PATCH v6 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops |
Date: |
Sun, 26 Sep 2021 01:30:20 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
tcg/loongarch64/tcg-target-con-set.h | 1 +
tcg/loongarch64/tcg-target.c.inc | 65 ++++++++++++++++++++++++++++
tcg/loongarch64/tcg-target.h | 16 +++----
3 files changed, 74 insertions(+), 8 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-con-set.h
b/tcg/loongarch64/tcg-target-con-set.h
index 4b8ce85897..fb56f3a295 100644
--- a/tcg/loongarch64/tcg-target-con-set.h
+++ b/tcg/loongarch64/tcg-target-con-set.h
@@ -23,3 +23,4 @@ C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 0e6b241097..67f07a3853 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -717,6 +717,55 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_mul_i32:
+ tcg_out_opc_mul_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_mul_i64:
+ tcg_out_opc_mul_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_mulsh_i32:
+ tcg_out_opc_mulh_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out_opc_mulh_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_muluh_i32:
+ tcg_out_opc_mulh_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_muluh_i64:
+ tcg_out_opc_mulh_du(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_div_i32:
+ tcg_out_opc_div_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_div_i64:
+ tcg_out_opc_div_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_divu_i32:
+ tcg_out_opc_div_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_divu_i64:
+ tcg_out_opc_div_du(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_rem_i32:
+ tcg_out_opc_mod_w(s, a0, a1, a2);
+ break;
+ case INDEX_op_rem_i64:
+ tcg_out_opc_mod_d(s, a0, a1, a2);
+ break;
+
+ case INDEX_op_remu_i32:
+ tcg_out_opc_mod_wu(s, a0, a1, a2);
+ break;
+ case INDEX_op_remu_i64:
+ tcg_out_opc_mod_du(s, a0, a1, a2);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
default:
@@ -808,6 +857,22 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_sub_i64:
return C_O1_I2(r, rZ, rN);
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_muluh_i64:
+ case INDEX_op_div_i32:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i32:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i32:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i32:
+ case INDEX_op_remu_i64:
+ return C_O1_I2(r, rZ, rZ);
+
default:
g_assert_not_reached();
}
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
index e59c2a7bec..2ac2c342c7 100644
--- a/tcg/loongarch64/tcg-target.h
+++ b/tcg/loongarch64/tcg-target.h
@@ -93,8 +93,8 @@ typedef enum {
/* optional instructions */
#define TCG_TARGET_HAS_movcond_i32 0
-#define TCG_TARGET_HAS_div_i32 0
-#define TCG_TARGET_HAS_rem_i32 0
+#define TCG_TARGET_HAS_div_i32 1
+#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_div2_i32 0
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
@@ -105,8 +105,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
-#define TCG_TARGET_HAS_muluh_i32 0
-#define TCG_TARGET_HAS_mulsh_i32 0
+#define TCG_TARGET_HAS_muluh_i32 1
+#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
@@ -130,8 +130,8 @@ typedef enum {
/* 64-bit operations */
#define TCG_TARGET_HAS_movcond_i64 0
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_div2_i64 0
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_deposit_i64 1
@@ -163,8 +163,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
-#define TCG_TARGET_HAS_muluh_i64 0
-#define TCG_TARGET_HAS_mulsh_i64 0
+#define TCG_TARGET_HAS_muluh_i64 1
+#define TCG_TARGET_HAS_mulsh_i64 1
/* not defined -- call should be eliminated at compile time */
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
--
2.33.0
- [PATCH v6 21/30] tcg/loongarch64: Implement tcg_out_call, (continued)
- [PATCH v6 21/30] tcg/loongarch64: Implement tcg_out_call, WANG Xuerui, 2021/09/25
- [PATCH v6 25/30] tcg/loongarch64: Implement exit_tb/goto_tb, WANG Xuerui, 2021/09/25
- [PATCH v6 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue, WANG Xuerui, 2021/09/25
- [PATCH v6 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts, WANG Xuerui, 2021/09/25
- [PATCH v6 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops, WANG Xuerui, 2021/09/25
- [PATCH v6 19/30] tcg/loongarch64: Implement br/brcond ops, WANG Xuerui, 2021/09/25
- [PATCH v6 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops, WANG Xuerui, 2021/09/25
- [PATCH v6 17/30] tcg/loongarch64: Implement add/sub ops, WANG Xuerui, 2021/09/25
- [PATCH v6 20/30] tcg/loongarch64: Implement setcond ops, WANG Xuerui, 2021/09/25
- [PATCH v6 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops,
WANG Xuerui <=
- [PATCH v6 22/30] tcg/loongarch64: Implement simple load/store ops, WANG Xuerui, 2021/09/25
- [PATCH v6 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops, WANG Xuerui, 2021/09/25
- [PATCH v6 30/30] configure, meson.build: Mark support for loongarch64 hosts, WANG Xuerui, 2021/09/25
- [PATCH v6 13/30] tcg/loongarch64: Implement deposit/extract ops, WANG Xuerui, 2021/09/25
- [PATCH v6 28/30] linux-user: Add safe syscall handling for loongarch64 hosts, WANG Xuerui, 2021/09/25
- [PATCH v6 27/30] tcg/loongarch64: Register the JIT, WANG Xuerui, 2021/09/25