Re: [PATCH 18/33] target/mips: Convert MSA 2R instruction format to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> +static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *a,
> +                         void (*gen_msa_2r_b)(TCGv_ptr, TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_2r_h)(TCGv_ptr, TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_2r_w)(TCGv_ptr, TCGv_i32, TCGv_i32),
> +                         void (*gen_msa_2r_d)(TCGv_ptr, TCGv_i32, TCGv_i32))
>   {
> -#define MASK_MSA_2R(op)     (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
> -                            (op & (0x7 << 18)))
> -    uint8_t ws = (ctx->opcode >> 11) & 0x1f;
> -    uint8_t wd = (ctx->opcode >> 6) & 0x1f;
> -    uint8_t df = (ctx->opcode >> 16) & 0x3;
> -    TCGv_i32 twd = tcg_const_i32(wd);
> -    TCGv_i32 tws = tcg_const_i32(ws);
> +    TCGv_i32 twd = tcg_const_i32(a->wd);
> +    TCGv_i32 tws = tcg_const_i32(a->ws);

tcg_constant_i32.

Missing check_msa_access.

> +    switch (a->df) {
> +    case DF_BYTE:
> +        if (gen_msa_2r_b == NULL) {
> +            gen_reserved_instruction(ctx);
> +        } else {
> +            gen_msa_2r_b(cpu_env, twd, tws);

Why the null check?


r~