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[PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configura
From: |
Alistair Francis |
Subject: |
[PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration |
Date: |
Fri, 29 Oct 2021 17:08:00 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Using a macro for the PLIC configuration doesn't make the code any
easier to read. Instead it makes it harder to figure out what is going
on, so let's remove it.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com
---
include/hw/riscv/virt.h | 1 -
hw/riscv/virt.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d9105c1886..b8ef99f348 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -73,7 +73,6 @@ enum {
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
};
-#define VIRT_PLIC_HART_CONFIG "MS"
#define VIRT_PLIC_NUM_SOURCES 127
#define VIRT_PLIC_NUM_PRIORITIES 7
#define VIRT_PLIC_PRIORITY_BASE 0x04
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index b3b431c847..28a5909a3b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -758,7 +758,7 @@ static char *plic_hart_config_string(int hart_count)
int i;
for (i = 0; i < hart_count; i++) {
- vals[i] = VIRT_PLIC_HART_CONFIG;
+ vals[i] = "MS";
}
vals[i] = NULL;
--
2.31.1
- [PULL v2 00/18] riscv-to-apply queue, Alistair Francis, 2021/10/29
- [PULL v2 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration,
Alistair Francis <=
- [PULL v2 02/18] hw/riscv: boot: Add a PLIC config string function, Alistair Francis, 2021/10/29
- [PULL v2 03/18] hw/riscv: sifive_u: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 05/18] hw/riscv: virt: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/29
- [PULL v2 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/29
- [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/29
- [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/29
- [PULL v2 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/29
- [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/29