Re: [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructio

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Re: [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructio

From:	Richard Henderson
Subject:	Re: [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions
Date:	Sat, 30 Oct 2021 20:49:52 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/25/21 5:28 AM, Frédéric Pétrot wrote:

+static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
+{
+    if (reg_num != 0) {
+        switch (get_ol(ctx)) {
+        case MXL_RV32:
+            tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
+            tcg_gen_ext32s_tl(cpu_gpr[reg_num], cpu_gpr[reg_num]);


tcg_gen_movi_tl(gpr, (int32_t)imm);

No extra ext32s required.  Otherwise,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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[PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, (continued)
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson, 2021/10/30
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 2021/10/30
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Philippe Mathieu-Daudé, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/25
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson, 2021/10/30
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Richard Henderson <=
- [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Richard Henderson, 2021/10/31
- [PATCH v4 14/17] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/25
- [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/25
- [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 13/17] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/25

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