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[PATCH v10 33/77] target/riscv: rvv-1.0: element index instruction
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From: |
frank . chang |
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Subject: |
[PATCH v10 33/77] target/riscv: rvv-1.0: element index instruction |
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Date: |
Mon, 29 Nov 2021 11:02:53 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3ac5162aeb7..ab274dcde12 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -633,7 +633,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111
@r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
-vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
+vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
--
2.25.1
- [PATCH v10 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load, (continued)
- [PATCH v10 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load, frank . chang, 2021/11/28
- [PATCH v10 24/77] target/riscv: rvv-1.0: load/store whole register instructions, frank . chang, 2021/11/28
- [PATCH v10 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, frank . chang, 2021/11/28
- [PATCH v10 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, frank . chang, 2021/11/28
- [PATCH v10 27/77] target/riscv: rvv-1.0: floating-point square-root instruction, frank . chang, 2021/11/28
- [PATCH v10 28/77] target/riscv: rvv-1.0: floating-point classify instructions, frank . chang, 2021/11/28
- [PATCH v10 29/77] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 2021/11/28
- [PATCH v10 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/11/28
- [PATCH v10 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/11/28
- [PATCH v10 32/77] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/11/28
- [PATCH v10 33/77] target/riscv: rvv-1.0: element index instruction,
frank . chang <=
- [PATCH v10 35/77] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/11/28
- [PATCH v10 36/77] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/11/28
- [PATCH v10 37/77] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/11/28
- [PATCH v10 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/11/28
- [PATCH v10 39/77] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/11/28
- [PATCH v10 40/77] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/11/28
- [PATCH v10 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/11/28
- [PATCH v10 42/77] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/11/28
- [PATCH v10 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/11/28
- [PATCH v10 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/11/28