Re: [PATCH 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}

[Alistair Francis]

On Fri, Dec 24, 2021 at 1:51 PM liweiwei <liweiwei@iscas.ac.cn> wrote:
>
> Co-authored-by: ardxwe <ardxwe@gmail.com>
> Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
> Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
> ---
>  roms/SLOF                |  2 +-
>  target/riscv/cpu.c       | 12 ++++++++++++
>  target/riscv/cpu.h       |  4 ++++
>  target/riscv/translate.c |  8 ++++++++
>  4 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/roms/SLOF b/roms/SLOF
> index a6906b024c..dd0dcaa1c1 160000
> --- a/roms/SLOF
> +++ b/roms/SLOF
> @@ -1 +1 @@
> -Subproject commit a6906b024c6cca5a86496f51eb4bfee3a0c36148
> +Subproject commit dd0dcaa1c1085c159ddab709c7f274b3917be8bd

It looks like you accidentally changed a submodule.

Alistair