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[PATCH v2 0/5] Improve RISC-V debugging support.
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From: |
Konrad Schwarz |
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Subject: |
[PATCH v2 0/5] Improve RISC-V debugging support. |
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Date: |
Tue, 4 Jan 2022 16:51:15 +0100 |
Added the files missing in v1 of this patch.
-- >8 --
1) Make the QEMU monitor `info registers' command more informative
2) Implement the QEMU monitor `print $register'
3) Introduce a new command `info gmem' to the QEMU monitor, which displays
a RISC-V hypervisor's guest's 2nd level paging tables similarly to the
existing `info mem' command.
4) Improve QEMU RISC-V target descriptions for GDB. In particular, add
type information for many control and status registers.
5) Extend the virtual `priv' register with hypervisor virtualization status.
Konrad Schwarz (5):
RISC-V: larger and more consistent register set for 'info registers'
RISC-V: monitor's print register functionality
RISC-V: 'info gmem' to show hypervisor guest -> physical address
translations
RISC-V: Typed CSRs in gdbserver
RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug
register
gdb-xml/riscv-32bit-virtual.xml | 30 ++-
gdb-xml/riscv-64bit-virtual.xml | 30 ++-
hmp-commands-info.hx | 16 ++
include/monitor/hmp-target.h | 2 +
target/riscv/cpu.c | 327 ++++++++++++++++++++++++++---
target/riscv/csr.c | 2 +
target/riscv/csr32-op-gdbserver.h | 109 ++++++++++
target/riscv/csr64-op-gdbserver.h | 76 +++++++
target/riscv/gdb_csr_type_group.c | 16 ++
target/riscv/gdb_csr_type_group.h | 3 +
target/riscv/gdb_csr_types.c | 333 ++++++++++++++++++++++++++++++
target/riscv/gdb_csr_types.h | 3 +
target/riscv/gdbstub.c | 31 ++-
target/riscv/meson.build | 4 +-
target/riscv/monitor.c | 204 ++++++++++++++----
15 files changed, 1115 insertions(+), 71 deletions(-)
create mode 100644 target/riscv/csr32-op-gdbserver.h
create mode 100644 target/riscv/csr64-op-gdbserver.h
create mode 100644 target/riscv/gdb_csr_type_group.c
create mode 100644 target/riscv/gdb_csr_type_group.h
create mode 100644 target/riscv/gdb_csr_types.c
create mode 100644 target/riscv/gdb_csr_types.h
base-commit: 8627edfb3f1fca24a96a0954148885c3241c10f8
--
Konrad Schwarz
- [PATCH v1 0/5] Improve RISC-V debugging support., Konrad Schwarz, 2022/01/02
- [PATCH v1 2/5] RISC-V: monitor's print register functionality, Konrad Schwarz, 2022/01/02
- [PATCH v1 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Konrad Schwarz, 2022/01/02
- [PATCH v1 1/5] RISC-V: larger and more consistent register set for 'info registers', Konrad Schwarz, 2022/01/02
- [PATCH v1 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register, Konrad Schwarz, 2022/01/02
- [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver, Konrad Schwarz, 2022/01/02
- Re: [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver, Ralf Ramsauer, 2022/01/03
- [PATCH v2 0/5] Improve RISC-V debugging support.,
Konrad Schwarz <=
- [PATCH v2 2/5] RISC-V: monitor's print register functionality, Konrad Schwarz, 2022/01/04
- [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Konrad Schwarz, 2022/01/04
- Re: [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Alistair Francis, 2022/01/04
- RE: [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations, Schwarz, Konrad, 2022/01/05
- [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Konrad Schwarz, 2022/01/04
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Alistair Francis, 2022/01/04
- RE: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Schwarz, Konrad, 2022/01/05
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Richard Henderson, 2022/01/04
- RE: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Schwarz, Konrad, 2022/01/05
- Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver, Richard Henderson, 2022/01/05