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[PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs
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From: |
Alistair Francis |
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Subject: |
[PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs |
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Date: |
Sat, 8 Jan 2022 15:50:12 +1000 |
From: Nikita Shubin <n.shubin@yadro.com>
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured and pmp is present, othwerwise access
should succeed.
Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is
configured)
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211214092659.15709-1-nikita.shubin@maquefel.me
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ee7c24efe7..58d992e98a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -146,7 +146,8 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong
cpu_pc_deb)
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
- if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
+ if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+ !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
--
2.31.1
- [PULL 00/37] riscv-to-apply queue, Alistair Francis, 2022/01/08
- [PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs,
Alistair Francis <=
- [PULL 02/37] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register, Alistair Francis, 2022/01/08
- [PULL 07/37] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2022/01/08
- [PULL 04/37] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2022/01/08
- [PULL 05/37] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2022/01/08
- [PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers, Alistair Francis, 2022/01/08
- [PULL 08/37] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2022/01/08
- [PULL 10/37] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2022/01/08
- [PULL 06/37] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2022/01/08
- [PULL 09/37] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2022/01/08
- [PULL 11/37] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2022/01/08