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[PULL 11/37] hw/riscv: virt: Allow support for 32 cores
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From: |
Alistair Francis |
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Subject: |
[PULL 11/37] hw/riscv: virt: Allow support for 32 cores |
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Date: |
Sat, 8 Jan 2022 15:50:22 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
let's set that as the maximum for the virt board.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-9-alistair.francis@opensource.wdc.com>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b8ef99f348..6e9f61ccd9 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
#include "hw/block/flash.h"
#include "qom/object.h"
-#define VIRT_CPUS_MAX 8
+#define VIRT_CPUS_MAX 32
#define VIRT_SOCKETS_MAX 8
#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
--
2.31.1
- [PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs, (continued)
- [PULL 01/37] target/riscv/pmp: fix no pmp illegal intrs, Alistair Francis, 2022/01/08
- [PULL 02/37] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register, Alistair Francis, 2022/01/08
- [PULL 07/37] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2022/01/08
- [PULL 04/37] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2022/01/08
- [PULL 05/37] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2022/01/08
- [PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers, Alistair Francis, 2022/01/08
- [PULL 08/37] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2022/01/08
- [PULL 10/37] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2022/01/08
- [PULL 06/37] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2022/01/08
- [PULL 09/37] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2022/01/08
- [PULL 11/37] hw/riscv: virt: Allow support for 32 cores,
Alistair Francis <=
- [PULL 12/37] roms/opensbi: Upgrade from v0.9 to v1.0, Alistair Francis, 2022/01/08
- [PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns, Alistair Francis, 2022/01/08
- [PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns, Alistair Francis, 2022/01/08
- [PULL 15/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns, Alistair Francis, 2022/01/08
- [PULL 16/37] target/riscv: Fix position of 'experimental' comment, Alistair Francis, 2022/01/08
- [PULL 18/37] exec/memop: Adding signed quad and octo defines, Alistair Francis, 2022/01/08
- [PULL 17/37] exec/memop: Adding signedness to quad definitions, Alistair Francis, 2022/01/08
- [PULL 19/37] qemu/int128: addition of div/rem 128-bit operations, Alistair Francis, 2022/01/08
- [PULL 20/37] target/riscv: additional macros to check instruction support, Alistair Francis, 2022/01/08
- [PULL 21/37] target/riscv: separation of bitwise logic and arithmetic helpers, Alistair Francis, 2022/01/08