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[PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check funct
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From: |
Alistair Francis |
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Subject: |
[PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns |
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Date: |
Sat, 8 Jan 2022 15:50:24 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220105022247.21131-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5e3f7fdb77..8d92243f2b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2254,7 +2254,8 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
- require_rvf(s) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
}
@@ -2292,7 +2293,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
- require_rvf(s) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_ds(s, a->rd, a->rs2, a->vm);
}
@@ -2321,7 +2323,8 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
- require_rvf(s) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
}
@@ -2359,7 +2362,8 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
- require_rvf(s) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8) &&
vext_check_isa_ill(s) &&
vext_check_dd(s, a->rd, a->rs2, a->vm);
}
--
2.31.1
- [PULL 07/37] hw/intc: sifive_plic: Cleanup remaining functions, (continued)
- [PULL 07/37] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2022/01/08
- [PULL 04/37] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2022/01/08
- [PULL 05/37] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2022/01/08
- [PULL 03/37] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers, Alistair Francis, 2022/01/08
- [PULL 08/37] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2022/01/08
- [PULL 10/37] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2022/01/08
- [PULL 06/37] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2022/01/08
- [PULL 09/37] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2022/01/08
- [PULL 11/37] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2022/01/08
- [PULL 12/37] roms/opensbi: Upgrade from v0.9 to v1.0, Alistair Francis, 2022/01/08
- [PULL 13/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns,
Alistair Francis <=
- [PULL 14/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp/int type-convert insns, Alistair Francis, 2022/01/08
- [PULL 15/37] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns, Alistair Francis, 2022/01/08
- [PULL 16/37] target/riscv: Fix position of 'experimental' comment, Alistair Francis, 2022/01/08
- [PULL 18/37] exec/memop: Adding signed quad and octo defines, Alistair Francis, 2022/01/08
- [PULL 17/37] exec/memop: Adding signedness to quad definitions, Alistair Francis, 2022/01/08
- [PULL 19/37] qemu/int128: addition of div/rem 128-bit operations, Alistair Francis, 2022/01/08
- [PULL 20/37] target/riscv: additional macros to check instruction support, Alistair Francis, 2022/01/08
- [PULL 21/37] target/riscv: separation of bitwise logic and arithmetic helpers, Alistair Francis, 2022/01/08
- [PULL 22/37] target/riscv: array for the 64 upper bits of 128-bit registers, Alistair Francis, 2022/01/08
- [PULL 23/37] target/riscv: setup everything for rv64 to support rv128 execution, Alistair Francis, 2022/01/08