[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 26/37] target/riscv: support for 128-bit bitwise instructions
|
From: |
Alistair Francis |
|
Subject: |
[PULL 26/37] target/riscv: support for 128-bit bitwise instructions |
|
Date: |
Sat, 8 Jan 2022 15:50:37 +1000 |
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-11-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d4cf965c9e..b43efc9bc3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -523,7 +523,15 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
func(dest, src1, a->imm);
- gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl(ctx) == MXL_RV128) {
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv desth = dest_gprh(ctx, a->rd);
+
+ func(desth, src1h, -(a->imm < 0));
+ gen_set_gpr128(ctx, a->rd, dest, desth);
+ } else {
+ gen_set_gpr(ctx, a->rd, dest);
+ }
return true;
}
@@ -537,7 +545,16 @@ static bool gen_logic(DisasContext *ctx, arg_r *a,
func(dest, src1, src2);
- gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl(ctx) == MXL_RV128) {
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv src2h = get_gprh(ctx, a->rs2);
+ TCGv desth = dest_gprh(ctx, a->rd);
+
+ func(desth, src1h, src2h);
+ gen_set_gpr128(ctx, a->rd, dest, desth);
+ } else {
+ gen_set_gpr(ctx, a->rd, dest);
+ }
return true;
}
--
2.31.1
- [PULL 16/37] target/riscv: Fix position of 'experimental' comment, (continued)
- [PULL 16/37] target/riscv: Fix position of 'experimental' comment, Alistair Francis, 2022/01/08
- [PULL 18/37] exec/memop: Adding signed quad and octo defines, Alistair Francis, 2022/01/08
- [PULL 17/37] exec/memop: Adding signedness to quad definitions, Alistair Francis, 2022/01/08
- [PULL 19/37] qemu/int128: addition of div/rem 128-bit operations, Alistair Francis, 2022/01/08
- [PULL 20/37] target/riscv: additional macros to check instruction support, Alistair Francis, 2022/01/08
- [PULL 21/37] target/riscv: separation of bitwise logic and arithmetic helpers, Alistair Francis, 2022/01/08
- [PULL 22/37] target/riscv: array for the 64 upper bits of 128-bit registers, Alistair Francis, 2022/01/08
- [PULL 23/37] target/riscv: setup everything for rv64 to support rv128 execution, Alistair Francis, 2022/01/08
- [PULL 25/37] target/riscv: accessors to registers upper part and 128-bit load/store, Alistair Francis, 2022/01/08
- [PULL 27/37] target/riscv: support for 128-bit U-type instructions, Alistair Francis, 2022/01/08
- [PULL 26/37] target/riscv: support for 128-bit bitwise instructions,
Alistair Francis <=
- [PULL 29/37] target/riscv: support for 128-bit arithmetic instructions, Alistair Francis, 2022/01/08
- [PULL 24/37] target/riscv: moving some insns close to similar insns, Alistair Francis, 2022/01/08
- [PULL 28/37] target/riscv: support for 128-bit shift instructions, Alistair Francis, 2022/01/08
- [PULL 30/37] target/riscv: support for 128-bit M extension, Alistair Francis, 2022/01/08
- [PULL 31/37] target/riscv: adding high part of some csrs, Alistair Francis, 2022/01/08
- [PULL 32/37] target/riscv: helper functions to wrap calls to 128-bit csr insns, Alistair Francis, 2022/01/08
- [PULL 33/37] target/riscv: modification of the trans_csrxx for 128-bit support, Alistair Francis, 2022/01/08
- [PULL 34/37] target/riscv: actual functions to realize crs 128-bit insns, Alistair Francis, 2022/01/08
- [PULL 35/37] target/riscv: Set the opcode in DisasContext, Alistair Francis, 2022/01/08
- [PULL 36/37] target/riscv: Fixup setting GVA, Alistair Francis, 2022/01/08