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[PULL 35/37] target/riscv: Set the opcode in DisasContext
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From: |
Alistair Francis |
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Subject: |
[PULL 35/37] target/riscv: Set the opcode in DisasContext |
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Date: |
Sat, 8 Jan 2022 15:50:46 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211220064916.107241-2-alistair.francis@opensource.wdc.com
---
target/riscv/translate.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4ae4345691..9e4f9c3342 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -846,6 +846,7 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
+ ctx->opcode = opcode;
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, opcode)) {
gen_exception_illegal(ctx);
@@ -856,6 +857,7 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
opcode32 = deposit32(opcode32, 16, 16,
translator_lduw(env, &ctx->base,
ctx->base.pc_next + 2));
+ ctx->opcode = opcode32;
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, opcode32)) {
gen_exception_illegal(ctx);
--
2.31.1
- [PULL 27/37] target/riscv: support for 128-bit U-type instructions, (continued)
- [PULL 27/37] target/riscv: support for 128-bit U-type instructions, Alistair Francis, 2022/01/08
- [PULL 26/37] target/riscv: support for 128-bit bitwise instructions, Alistair Francis, 2022/01/08
- [PULL 29/37] target/riscv: support for 128-bit arithmetic instructions, Alistair Francis, 2022/01/08
- [PULL 24/37] target/riscv: moving some insns close to similar insns, Alistair Francis, 2022/01/08
- [PULL 28/37] target/riscv: support for 128-bit shift instructions, Alistair Francis, 2022/01/08
- [PULL 30/37] target/riscv: support for 128-bit M extension, Alistair Francis, 2022/01/08
- [PULL 31/37] target/riscv: adding high part of some csrs, Alistair Francis, 2022/01/08
- [PULL 32/37] target/riscv: helper functions to wrap calls to 128-bit csr insns, Alistair Francis, 2022/01/08
- [PULL 33/37] target/riscv: modification of the trans_csrxx for 128-bit support, Alistair Francis, 2022/01/08
- [PULL 34/37] target/riscv: actual functions to realize crs 128-bit insns, Alistair Francis, 2022/01/08
- [PULL 35/37] target/riscv: Set the opcode in DisasContext,
Alistair Francis <=
- [PULL 36/37] target/riscv: Fixup setting GVA, Alistair Francis, 2022/01/08
- [PULL 37/37] target/riscv: Implement the stval/mtval illegal instruction, Alistair Francis, 2022/01/08
- Re: [PULL 00/37] riscv-to-apply queue, Richard Henderson, 2022/01/08