RE: [RFC PATCH 2/7] x86: Add AMX XTILECFG and XTILEDATA components

[Tian, Kevin]

> From: Zhong, Yang <yang.zhong@intel.com>
> Sent: Friday, January 7, 2022 5:31 PM
> 
> From: Jing Liu <jing2.liu@intel.com>
> 
> AMX XTILECFG and XTILEDATA are managed by XSAVE feature
> set. State component 17 is used for 64-byte TILECFG register
> (XTILECFG state) and component 18 is used for 8192 bytes
> of tile data (XTILEDATA state).

to be consistent, "tile data" -> "TILEDATA"

> 
> Add AMX feature bits to x86_ext_save_areas array to set
> up AMX components. Add structs that define the layout of
> AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
> structs sizes.
> 
> Signed-off-by: Jing Liu <jing2.liu@intel.com>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---
>  target/i386/cpu.h | 16 +++++++++++++++-
>  target/i386/cpu.c |  8 ++++++++
>  2 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 7f9700544f..768a8218be 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -537,6 +537,8 @@ typedef enum X86Seg {
>  #define XSTATE_ZMM_Hi256_BIT            6
>  #define XSTATE_Hi16_ZMM_BIT             7
>  #define XSTATE_PKRU_BIT                 9
> +#define XSTATE_XTILE_CFG_BIT            17
> +#define XSTATE_XTILE_DATA_BIT           18
> 
>  #define XSTATE_FP_MASK                  (1ULL << XSTATE_FP_BIT)
>  #define XSTATE_SSE_MASK                 (1ULL << XSTATE_SSE_BIT)
> @@ -1343,6 +1345,16 @@ typedef struct XSavePKRU {
>      uint32_t padding;
>  } XSavePKRU;
> 
> +/* Ext. save area 17: AMX XTILECFG state */
> +typedef struct XSaveXTILE_CFG {

remove "_"?

> +    uint8_t xtilecfg[64];
> +} XSaveXTILE_CFG;
> +
> +/* Ext. save area 18: AMX XTILEDATA state */
> +typedef struct XSaveXTILE_DATA {

ditto

> +    uint8_t xtiledata[8][1024];
> +} XSaveXTILE_DATA;
> +
>  QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
>  QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
>  QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
> @@ -1350,6 +1362,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=
> 0x40);
>  QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
>  QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
>  QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
> +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILE_CFG) != 0x40);
> +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILE_DATA) != 0x2000);
> 
>  typedef struct ExtSaveArea {
>      uint32_t feature, bits;
> @@ -1357,7 +1371,7 @@ typedef struct ExtSaveArea {
>      uint32_t need_align;
>  } ExtSaveArea;
> 
> -#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1)
> +#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
> 
>  extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 47bc4d5c1a..dd2c919c33 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1401,6 +1401,14 @@ ExtSaveArea
> x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
>      [XSTATE_PKRU_BIT] =
>            { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
>              .size = sizeof(XSavePKRU) },
> +    [XSTATE_XTILE_CFG_BIT] = {
> +        .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
> +        .size = sizeof(XSaveXTILE_CFG),
> +    },
> +    [XSTATE_XTILE_DATA_BIT] = {
> +        .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
> +        .size = sizeof(XSaveXTILE_DATA),
> +    },
>  };
> 
>  static uint32_t xsave_area_size(uint64_t mask)